公开(公告)号：US06870373B2

公开(公告)日：2005-03-22

申请号：US10236889

申请日：2002-09-06

申请人： Ute Kollmer ,  Stephan Sauter ,  Carsten Linnenbank ,  Roland Thewes

发明人： Ute Kollmer ,  Stephan Sauter ,  Carsten Linnenbank ,  Roland Thewes

IPC分类号： G11C7/06 ,  G11C11/405 ,  G11C11/4091 ,  G01R31/11 ,  G01R27/26

CPC分类号： G11C7/06 ,  G11C11/405 ,  G11C11/4091 ,  G11C2207/063

摘要： A circuit configuration for assessing capacitances in a matrix, which has a number of rows with at least one capacitance in at least one dimension, includes a test arm connected to first electrodes of each of the capacitances to be assessed and by which two different potentials can be applied to the first electrodes, a measurement arm connected to second electrodes of each of the capacitances to be assessed and that has a first measurement path and a second measurement path connected to a common potential. The first measurement path has an instrument for assessing the capacitances and the first and second measurement paths can be connected to the second electrodes. The circuit configuration has a drive device that connects each of the capacitances to be assessed individually to the two different potentials.

摘要翻译： 用于评估在至少一维中具有至少一个电容的行数的矩阵中的电容的电路配置包括连接到要评估的每个电容的第一电极的测试臂，并且两个不同的电位可以被 施加到第一电极，测量臂连接到要评估的每个电容的第二电极，并且具有连接到公共电位的第一测量路径和第二测量路径。 第一测量路径具有用于评估电容的仪器，并且第一和第二测量路径可以连接到第二电极。 电路配置具有驱动装置，其将要被分别评估的每个电容连接到两个不同的电位。

公开(公告)号：US06873173B2

公开(公告)日：2005-03-29

申请号：US10220449

申请日：2001-03-05

申请人： Ute Kollmer ,  Ulrich Schaper ,  Carsten Linnenbank ,  Roland Thewes

发明人： Ute Kollmer ,  Ulrich Schaper ,  Carsten Linnenbank ,  Roland Thewes

IPC分类号： G01R31/26 ,  G01R31/27 ,  G01R31/30 ,  G11C29/50

CPC分类号： G11C29/028 ,  G01R31/2621 ,  G01R31/275 ,  G01R31/3004 ,  G11C29/50 ,  G11C2029/5004

摘要： The invention relates to a test circuit configuration. Every gate terminal of a transistor to be tested is coupled to a gate voltage source in such a manner that the gate voltage can be measured and adjusted individually on every gate terminal. The source terminal of every transistor to be tested can be coupled to the source voltage source in such a manner that the source voltage can be measured and adjusted individually on every source terminal.

摘要翻译： 本发明涉及一种测试电路结构。 要测试的晶体管的每个栅极端子以这样的方式耦合到栅极电压源，使得可以在每个栅极端子上单独地测量和调整栅极电压。 要测试的每个晶体管的源极端子可以以这样的方式耦合到源极电压源，使得可以在每个源极端子上单独测量和调节源极电压。

公开(公告)号：US06831474B2

公开(公告)日：2004-12-14

申请号：US10203179

申请日：2002-12-30

申请人： Ute Kollmer ,  Carsten Linnenbank ,  Ulrich Schaper ,  Roland Thewes

发明人： Ute Kollmer ,  Carsten Linnenbank ,  Ulrich Schaper ,  Roland Thewes

IPC分类号： G01R3128

CPC分类号： G01R31/275 ,  G01R31/2851

摘要： An apparatus and method for testing a plurality of electrical components that are coupled to one another. Further, an electrical selection unit, coupled to the electrical components to be tested, is provided for selecting at least one electrical component to be tested. A parasitic voltage drop in the testing circuit can be at least partially compensated using a control element coupled to the electrical components to be tested. The invention makes it possible, for testing of electrical components on a wafer over a large distance, i.e., several millimeters, to permit automated compensation of interference influences which occur as a result of the lines coupling or connecting the components to be tested.

摘要翻译： 一种用于测试彼此耦合的多个电气部件的装置和方法。 此外，提供耦合到要测试的电气部件的电选择单元，用于选择至少一个要测试的电气部件。 可以使用耦合到要测试的电气部件的控制元件来至少部分地补偿测试电路中的寄生电压降。 本发明使得可以在大范围（即几毫米）上测试晶片上的电气部件，以允许自动补偿由于线路耦合或连接待测组件的结果而发生的干扰影响。

公开(公告)号：US6097661A

公开(公告)日：2000-08-01

申请号：US161004

申请日：1998-09-25

申请人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu ,  Ute Kollmer ,  Andreas Luck, deceased ,  by Manfred Luck, legal representative ,  by Inge Booken, legal representative

发明人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu ,  Ute Kollmer ,  Andreas Luck, deceased ,  by Manfred Luck, legal representative ,  by Inge Booken, legal representative

IPC分类号： G11C19/28 ,  G11C7/10 ,  G11C8/04 ,  G11C7/00

CPC分类号： G11C7/1018 ,  G11C8/04

摘要： In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.

摘要翻译： 在指针电路中，只有一个静态存储器（1）分别分别分配给每个输出（...，An-1，An，An + 1，...），其中每个分别具有一对相互补充的存储器 端子（Q，+ E，ovs Q + EE）。 两个终端处于彼此不同的两个存储的逻辑状态（“1”，“0”）。 每个存储器的存储器端子（Q）与分配给该存储器的输出端连接。 存储器由时钟信号控制。 这导致有利的表面要求和功率损耗低以及高速度。