公开(公告)号：US20050111536A1

公开(公告)日：2005-05-26

申请号：US10720974

申请日：2003-11-24

申请人： Hayden Cranford ,  Marcel Kossel ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Marcel Kossel ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H04B3/46 ,  H04L1/20 ,  H04L25/06

CPC分类号： H04L25/068 ,  H04B3/462 ,  H04L1/205

摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.

摘要翻译： 根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。 确定该部分中的边缘总数。 分析相邻的样本值，并从中形成统计值。 从统计值和总边缘数确定品质因数。 最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。

公开(公告)号：US20060008042A1

公开(公告)日：2006-01-12

申请号：US11225600

申请日：2005-09-13

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Paul Owczarski ,  Martin Schmatz ,  Joseph Stevens

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Paul Owczarski ,  Martin Schmatz ,  Joseph Stevens

IPC分类号： H03D3/24

CPC分类号： H03L7/0995 ,  H04L7/0004 ,  H04L7/0337

摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

摘要翻译： 本发明涉及包括逻辑发射机部分和逻辑接收机部分的统一数字架构。 提供了一种用于在包括发射机和接收机部分的有线媒体上传输数字数据的统一的串行链路系统和方法，发射机部分和接收机部分之一包括锁相环（PLL）电路。 PLL电路包括压控振荡器，分频器，相频检测器，电荷泵和多极环路滤波器。 一个实施例包括具有数字粗略回路和模拟精细回路的双回路PLL。

公开(公告)号：US20070242741A1

公开(公告)日：2007-10-18

申请号：US11405997

申请日：2006-04-18

申请人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

发明人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03H7/30

CPC分类号： H04L25/03063

摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

公开(公告)号：US20060029177A1

公开(公告)日：2006-02-09

申请号：US11249851

申请日：2005-10-13

申请人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03D3/24

CPC分类号： H03L7/08 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/10 ,  H04L7/0337 ,  H04L2027/0067

摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

公开(公告)号：US20080112521A1

公开(公告)日：2008-05-15

申请号：US11966438

申请日：2007-12-28

申请人： Martin Schmatz ,  Hayden Cranford ,  Vernon Norman

发明人： Martin Schmatz ,  Hayden Cranford ,  Vernon Norman

IPC分类号： H04L7/00

CPC分类号： H03L7/091 ,  H03L7/0814 ,  H03L7/089 ,  H04L7/0331

摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

摘要翻译： 本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。 时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。 它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。 设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。 相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

公开(公告)号：US20050195863A1

公开(公告)日：2005-09-08

申请号：US10791175

申请日：2004-03-02

申请人： Hayden Cranford ,  Gareth Nicholls ,  Bobak Modaress-Razavi ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Gareth Nicholls ,  Bobak Modaress-Razavi ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03L7/07 ,  H03L7/081 ,  H03L7/093 ,  H04L27/00 ,  H04J3/06

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H04L2027/0065 ,  H04L2027/0067

摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.

摘要翻译： 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。

公开(公告)号：US20060045224A1

公开(公告)日：2006-03-02

申请号：US10915790

申请日：2004-08-11

申请人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

发明人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/091 ,  H03L2207/50

摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.

摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。

公开(公告)号：US20050076279A1

公开(公告)日：2005-04-07

申请号：US10680679

申请日：2003-10-07

申请人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

IPC分类号： G01R31/317 ,  G06K5/04 ,  G01R31/28

CPC分类号： G01R31/31901 ,  G01R31/31707

摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.

摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。

公开(公告)号：US20070075785A1

公开(公告)日：2007-04-05

申请号：US11469423

申请日：2006-08-31

申请人： Marcel Kossel ,  Thomas Morf ,  Martin Schmatz ,  Silvan Wehrli

发明人： Marcel Kossel ,  Thomas Morf ,  Martin Schmatz ,  Silvan Wehrli

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/089 ,  H03L7/18

摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.

摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。

公开(公告)号：US20070061665A1

公开(公告)日：2007-03-15

申请号：US11214161

申请日：2005-08-29

申请人： Hayden Cranford ,  Martin Schmatz ,  Thomas Toifl

发明人： Hayden Cranford ,  Martin Schmatz ,  Thomas Toifl

IPC分类号： H03M13/00

CPC分类号： H03M13/336 ,  H03L7/091 ,  H04L1/0053 ,  H04L1/0061 ,  H04L7/033 ,  H04L7/048

摘要： The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).

摘要翻译： 根据本发明的基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟（sclk）触发的接收数据的数据锁存器（16）。 该系统还包括用于确定采样的接收数据是否以及哪个是错误的并且用于产生相位/频率校正信号（ctrl）的错误确定单元（20,21）。 此外，该系统包括用于根据校正信号（ctrl）产生采样时钟（sclk）的时钟发生器（23,24,25）。