公开(公告)号：US07808089B2

公开(公告)日：2010-10-05

申请号：US11959412

申请日：2007-12-18

申请人： Luu T. Nguyen ,  Vijaylaxmi Gumaste

发明人： Luu T. Nguyen ,  Vijaylaxmi Gumaste

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/27013 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83136 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One aspect of the invention pertains to a semiconductor package having a die and a die attach pad with a plurality of spaced apart pedestals supported by a web. A die is mounted on the die attach pad such that the die is supported by at least a plurality of the pedestals. Selected edge regions of the die are arranged to overlie recessed regions of the die attach pad between adjacent pedestals. The die is electrically connected to at least some of the contact leads. An adhesive is arranged to secure the die to the die attach pad, with the thickness of the adhesive between the web of the die attach pad and the die being greater than the thickness of the adhesive between the die and the top surfaces of the pedestals that support the die. The die attach pad may have rounded peripheral corners between adjacent edge surfaces of the die attach pad. In another aspect of the invention, a method of packaging integrated circuits is described, wherein the resulting packages include at least some of the aforementioned leadframe structures.

摘要翻译： 本发明的一个方面涉及具有管芯和管芯附接垫的半导体封装，其具有由幅材支撑的多个间隔开的基座。 模具安装在管芯附接垫上，使得管芯由至少多个基座支撑。 芯片的选定边缘区域被布置成覆盖在相邻基座之间的管芯附接焊盘的凹陷区域。 模具电连接到至少一些接触引线。 粘合剂被布置成将管芯固定到管芯附接垫上，其中管芯附接垫和管芯之间的粘合剂的厚度大于管芯和基座顶表面之间的粘合剂的厚度， 支持死亡 管芯附接垫可以在管芯附接垫的相邻边缘表面之间具有圆形的周边拐角。 在本发明的另一方面，描述了封装集成电路的方法，其中所得到的封装包括至少一些上述引线框结构。

公开(公告)号：US07385297B1

公开(公告)日：2008-06-10

申请号：US11274903

申请日：2005-11-14

申请人： Vijaylaxmi Gumaste ,  Anindya Poddar

发明人： Vijaylaxmi Gumaste ,  Anindya Poddar

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015

摘要： An under bond pad structure is described for integrated circuit dice are that have active circuits located below at least some of the bond pads. The metallization layers interconnection structures within the die are arranged so that electrically conductive vias do not extend between the bond pads and any underlying metallization layer in a region that overlies an active circuit. In some embodiments, no conductive vias are provided between any of the metallization layers in regions that underlie the bond pads and overlie an active circuit. The described arrangements significantly improve the resistance to cracking in the dielectric layers beneath the bond pad (and particularly the topmost intermediate dielectric layer) when wire bonding is used to electrically connect such dice within a package.

摘要翻译： 对于具有位于至少一些接合焊盘下方的有源电路的集成电路芯片，描述了接合焊盘结构。 管芯内的金属化层互连结构被布置成使得导电通孔不会在覆盖有源电路的区域中的接合焊盘和任何下面的金属化层之间延伸。 在一些实施例中，在位于接合焊盘之下的区域中的任何金属化层之间没有提供导电通孔并覆盖有源电路。 当引线接合用于将这种骰子电连接在封装内时，所描述的布置显着地改善了接合焊盘（特别是最上面的中间介电层）下方的电介质层的抗开裂性。

公开(公告)号：US20090152691A1

公开(公告)日：2009-06-18

申请号：US11959412

申请日：2007-12-18

申请人： Luu T. NGUYEN ,  Vijaylaxmi GUMASTE

发明人： Luu T. NGUYEN ,  Vijaylaxmi GUMASTE

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/27013 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83136 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One aspect of the invention pertains to a semiconductor package having a die and a die attach pad with a plurality of spaced apart pedestals supported by a web. A die is mounted on the die attach pad such that the die is supported by at least a plurality of the pedestals. Selected edge regions of the die are arranged to overlie recessed regions of the die attach pad between adjacent pedestals. The die is electrically connected to at least some of the contact leads. An adhesive is arranged to secure the die to the die attach pad, with the thickness of the adhesive between the web of the die attach pad and the die being greater than the thickness of the adhesive between the die and the top surfaces of the pedestals that support the die. The die attach pad may have rounded peripheral corners between adjacent edge surfaces of the die attach pad. In another aspect of the invention, a method of packaging integrated circuits is described, wherein the resulting packages include at least some of the aforementioned leadframe structures.

摘要翻译： 本发明的一个方面涉及具有管芯和管芯附接垫的半导体封装，其具有由幅材支撑的多个间隔开的基座。 模具安装在管芯附接垫上，使得管芯由至少多个基座支撑。 芯片的选定边缘区域被布置成覆盖在相邻基座之间的管芯附接焊盘的凹陷区域。 模具电连接到至少一些接触引线。 粘合剂被布置成将管芯固定到管芯附接垫上，其中管芯附接垫和管芯之间的粘合剂的厚度大于管芯和基座顶表面之间的粘合剂的厚度， 支持死亡 管芯附接垫可以在管芯附接垫的相邻边缘表面之间具有圆形的周边拐角。 在本发明的另一方面，描述了封装集成电路的方法，其中所得到的封装包括至少一些上述引线框结构。

公开(公告)号：US20090152683A1

公开(公告)日：2009-06-18

申请号：US11959422

申请日：2007-12-18

申请人： Luu T. Nguyen ,  Vijaylaxmi Gumaste

发明人： Luu T. Nguyen ,  Vijaylaxmi Gumaste

IPC分类号： H01L29/06 ,  H01L21/304 ,  H01L23/495

CPC分类号： H01L29/0657 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512

摘要： One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the invention, the sharpness of other corners and edges in the die are reduced. For example, reducing the sharpness of the bottom edge corners formed by the intersection of a sidewall and the back surface of a die can further diminish stress accumulations. One embodiment pertains to a wafer carried on a wafer support, where the wafer includes a multiplicity of such dice. Another embodiment involves a semiconductor package containing such dice. Methods of fabricating the dice are also described.

摘要翻译： 本发明的一个方面涉及具有圆形侧壁连接边缘拐角的半导体管芯。 这种倒圆减少了这些角落处的压力积聚。 在本发明的其它实施例中，模具中其他角部和边缘的清晰度降低。 例如，降低由侧壁与模具的背面相交形成的底部边角的锐度可进一步减小应力积聚。 一个实施例涉及承载在晶片支撑件上的晶片，其中晶片包括多个这样的骰子。 另一实施例涉及包含这种骰子的半导体封装。 还描述了制造骰子的方法。