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    Methods and apparatus for white space reduction in a production facility
    1.
    发明授权
    Methods and apparatus for white space reduction in a production facility 有权
    在生产设施中减少空白空间的方法和装置

    公开(公告)号：US08160736B2

    公开(公告)日：2012-04-17

    申请号：US12023037

    申请日：2008-01-31

    申请人： Thangappan Krisnamuthi ,  Mohd Azizi Chik ,  Tin Tin Ung ,  Kian Wee Lim ,  Stephen Todd Markle

    发明人： Thangappan Krisnamuthi ,  Mohd Azizi Chik ,  Tin Tin Ung ,  Kian Wee Lim ,  Stephen Todd Markle

    IPC分类号： G06F19/00

    CPC分类号： G06Q10/08 ,  G06Q10/06

    摘要： Efficient manufacturing automation system and methods are described. The automation system controls movement of materials for processing by tools in a manufacturing facility. The system and methods include pre-emptive dispatching for transferring of materials. With the pre-emptive dispatching, the next destination and next lot to be processed is determined prior to a first lot being converted to a ready to unload state. This reduces wait time or idle time to improve tool utilization.

    摘要翻译： 描述了高效的制造自动化系统和方法。 自动化系统控制通过制造设备中的工具进行处理的材料的移动。 系统和方法包括用于材料转移的优先调度。 通过优先调度，在将第一批次转换为准备卸载状态之前确定要处理的下一个目的地和下一个批次。 这减少了等待时间或空闲时间，从而提高了工具利用率。

    METHODS AND APPARATUS FOR WHITE SPACE REDUCTION IN A PRODUCTION FACILITY
    3.
    发明申请
    METHODS AND APPARATUS FOR WHITE SPACE REDUCTION IN A PRODUCTION FACILITY 有权
    在生产设施中减少白色空间的方法和装置

    公开(公告)号：US20080183324A1

    公开(公告)日：2008-07-31

    申请号：US12023037

    申请日：2008-01-31

    申请人： Thangappan Krisnamuthi ,  Mohd Azizi CHIK ,  Tin Tin UNG ,  Kian Wee LIM ,  Stephen Todd MARKLE

    发明人： Thangappan Krisnamuthi ,  Mohd Azizi CHIK ,  Tin Tin UNG ,  Kian Wee LIM ,  Stephen Todd MARKLE

    IPC分类号： G06F17/00

    CPC分类号： G06Q10/08 ,  G06Q10/06

    摘要： Efficient manufacturing automation system and methods are described. The automation system controls movement of materials for processing by tools in a manufacturing facility. The system and methods include pre-emptive dispatching for transferring of materials. With the pre-emptive dispatching, the next destination and next lot to be processed is determined prior to a first lot being converted to a ready to unload state. This reduces wait time or idle time to improve tool utilization.

    摘要翻译： 描述了高效的制造自动化系统和方法。 自动化系统控制通过制造设备中的工具进行处理的材料的移动。 系统和方法包括用于材料转移的优先调度。 通过优先调度，在将第一批次转换为准备卸载状态之前确定要处理的下一个目的地和下一个批次。 这减少了等待时间或空闲时间，从而提高了工具利用率。

    Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
    5.
    发明授权
    Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
    氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件

    公开(公告)号：US06297126B1

    公开(公告)日：2001-10-02

    申请号：US09351240

    申请日：1999-07-12

    申请人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

    发明人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232 ,  H01L21/76897

    摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.

    摘要翻译： 具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。 氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。 形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。 在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。 防止导电钨金属插塞的后续处理被钝化沟槽盖短路。 这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。 此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。 此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

    Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
    6.
    发明授权
    Method to form shallow trench isolations with rounded corners and reduced trench oxide recess 有权
    形成具有圆角和减少的沟槽氧化物凹陷的浅沟槽隔离的方法

    公开(公告)号：US06228727B1

    公开(公告)日：2001-05-08

    申请号：US09405061

    申请日：1999-09-27

    申请人： Chong Wee Lim ,  Soh Yun Siah ,  Eng Hua Lim ,  Kong-Hean Lee ,  Chun Hui Low

    发明人： Chong Wee Lim ,  Soh Yun Siah ,  Eng Hua Lim ,  Kong-Hean Lee ,  Chun Hui Low

    IPC分类号： H01L21336

    CPC分类号： H01L21/3086 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/32 ,  H01L21/76232

    摘要： A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.

    摘要翻译： 已经实现了制造浅沟槽隔离的方法。 提供半导体衬底。 生长覆盖半导体衬底的焊盘氧化物层。 沉积氮化硅层。 将氮化硅层和焊盘氧化物层图案化以形成硬掩模。 硬掩模中的开口对应于半导体衬底中的规划沟槽。 沉积氮化硅层和半导体衬底上的二氧化硅层。 二氧化硅层被各向异性地蚀刻以在硬掩模的开口的内侧上形成侧壁间隔物。 蚀刻半导体衬底以形成沟槽。 蚀刻掉侧壁间隔物。 对半导体衬底进行溅射蚀刻以使沟槽的角落四周。 生长在半导体衬底上的氧化物沟槽衬里层。 沉积氮化硅层并填充沟槽的沟槽填充层。 沟槽填充层被抛光到氮化硅层的顶表面。 蚀刻掉氮化硅层。 沟槽填充层和焊盘氧化物层被抛光到半导体衬底的顶表面以完成浅沟槽隔离，并且集成电路器件完成。

    Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device
    7.
    发明授权
    Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device 失效
    亚0.18微米水银CMOS器件制造低泄漏架构的方法

    公开(公告)号：US6165871A

    公开(公告)日：2000-12-26

    申请号：US356003

    申请日：1999-07-16

    申请人： Eng Hua Lim ,  Chong Wee Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Pei Ching Lee

    发明人： Eng Hua Lim ,  Chong Wee Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Pei Ching Lee

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8234

    CPC分类号： H01L29/665 ,  H01L21/76232 ,  H01L21/823481

    摘要： A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduces contact leakage.

    摘要翻译： 描述了形成阶梯式浅沟槽隔离的方法。 衬垫氧化物层沉积在半导体衬底的表面上。 沉积在衬垫氧化物层上的第一氮化物层。 蚀刻第一氮化物层，其中未被掩模覆盖，以提供衬垫氧化物层的开口。 通过开口内的衬垫氧化物层蚀刻第一沟槽并进入半导体衬底。 沉积第二氮化物层，覆盖第一氮化物层并填充第一沟槽。 同时，第二氮化物层被各向异性蚀刻以在第一沟槽的侧壁上形成氮化物间隔物，并且半导体衬底被蚀刻到不被间隔物覆盖的区域中以形成第二沟槽。 离子被注入到第二沟槽下面的半导体衬底中。 第一和第二沟槽填充有氧化物层。 此后，去除在制造集成电路器件时完成形成浅沟槽隔离的第一氮化物层和衬垫氧化物层。 该氮化物间隔物STI结构防止了STI拐角氧化物凹陷并且实现无边界接触形成。 这种独特的工艺可减少结漏电流并减少接触泄漏。

    Methods for elimination of arsenic based defects in semiconductor devices with isolation regions
    8.
    发明授权
    Methods for elimination of arsenic based defects in semiconductor devices with isolation regions 有权
    在具有隔离区域的半导体器件中消除基于砷的缺陷的方法

    公开(公告)号：US07268048B2

    公开(公告)日：2007-09-11

    申请号：US10913214

    申请日：2004-08-06

    申请人： Yin-Min Felicia Goh ,  Simon Chooi ,  Teck Wee Lim ,  Vincent Sih ,  Chian Yuh Sin ,  Ping Yu Ee ,  Zainab Ismail ,  Cher Sian Chua

    发明人： Yin-Min Felicia Goh ,  Simon Chooi ,  Teck Wee Lim ,  Vincent Sih ,  Chian Yuh Sin ,  Ping Yu Ee ,  Zainab Ismail ,  Cher Sian Chua

    IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/302

    CPC分类号： H01L21/02057 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/76237 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/7833

    摘要： Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation. Methods include wet etch procedures featuring hydrofluoric acid and hydrogen peroxide, as well as spin dry and dry etch procedures both employed post hydrofluoric acid treatment to remove re-deposited arsenic based defects.

    摘要翻译： 已经开发了制备用于硅化程序的源极/漏极区域的导电区域的方法。 该方法在沉积随后形成的金属硅化物区域的金属组分之前，特征在于去除自然氧化物以及从导电表面去除沉积的基于砷的缺陷。 注入用于N型源极/漏极区域的砷离子也被注入绝缘体区域，例如绝缘体填充的浅沟槽隔离区域。 用作预硅化物制备方法的组分的氢氟酸循环可以以基于砷的缺陷的形式从浅沟槽隔离区释放砷，其又可以沉积在源极/漏极区的表面上。 因此，本发明中描述的预硅化制备处理在金属硅化物形成之前特征是从导电表面除去天然氧化物和砷的缺陷。 方法包括以氢氟酸和过氧化氢为特征的湿法蚀刻程序，以及在氢氟酸处理之后采用的旋转干燥和干蚀刻方法，以去除重新沉积的基于砷的缺陷。

    Method and system for power management of an optical mouse
    9.
    发明申请
    Method and system for power management of an optical mouse 审中-公开
    光电鼠标电源管理方法及系统

    公开(公告)号：US20050206613A1

    公开(公告)日：2005-09-22

    申请号：US10803598

    申请日：2004-03-17

    申请人： Wai Chan ,  Wee Lim ,  Chun Wong

    发明人： Wai Chan ,  Wee Lim ,  Chun Wong

    IPC分类号： G09G5/00

    CPC分类号： G06F1/3203 ,  G06F1/3259 ,  Y02D10/155

    摘要： A system and method for power management of an optical mouse. A mechanical displacement sensor associated with the optical mouse is used to detect movement of the optical mouse. When the optical mouse is motionless, a switch within the mechanical displacement sensor sets the optical mouse to a standby state. The standby state conserves power. When motion is detected by the mechanical displacement sensor, the switch powers up the optical mouse into its normal mode of operation.

    摘要翻译： 一种用于光电鼠标的电源管理的系统和方法。 使用与光学鼠标相关联的机械位移传感器来检测光学鼠标的移动。 当光学鼠标静止时，机械位移传感器内的开关将光学鼠标设置为待机状态。 待机状态保存电源。 当通过机械位移传感器检测到运动时，开关将光电鼠标加电到其正常操作模式。

    Epitaxial CoSi2 on MOS devices
    10.
    发明授权
    Epitaxial CoSi2 on MOS devices 失效
    外延CoSi2在MOS器件上

    公开(公告)号：US06846359B2

    公开(公告)日：2005-01-25

    申请号：US10280668

    申请日：2002-10-25

    申请人： Chong Wee Lim ,  Chan Soo Shin ,  Ivan Georgiev Petrov ,  Joseph E. Greene

    发明人： Chong Wee Lim ,  Chan Soo Shin ,  Ivan Georgiev Petrov ,  Joseph E. Greene

    IPC分类号： C30B1/00 ,  C30B25/02 ,  G30B25/04

    CPC分类号： C30B1/00 ,  C30B25/02 ,  C30B29/10

    摘要： An SixNy or SiOxNy liner is formed on a MOS device. Cobalt is then deposited and reacts to form an epitaxial CoSi2 layer underneath the liner. The CoSi2 layer may be formed through a solid phase epitaxy or reactive deposition epitaxy salicide process. In addition to high quality epitaxial CoSi2 layers, the liner formed during the invention can protect device portions during etching processes used to form device contacts. The liner can act as an etch stop layer to prevent excessive removal of the shallow trench isolation, and protect against excessive loss of the CoSi2 layer.

    摘要翻译： 在MOS器件上形成SixNy或SiOxNy衬垫。 然后沉积钴并且反应以在衬垫下方形成外延CoSi 2层。 可以通过固相外延或反应性沉积外延自对准硅化物工艺形成CoSi 2层。 除了高质量的外延CoSi2层之外，本发明中形成的衬垫还可以在用于形成器件触点的蚀刻工艺期间保护器件部分。 衬里可以用作蚀刻停止层，以防止浅沟槽隔离物的过度去除，并且防止CoSi2层的过度损耗。