公开(公告)号：US6165871A

公开(公告)日：2000-12-26

申请号：US356003

申请日：1999-07-16

申请人： Eng Hua Lim ,  Chong Wee Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Pei Ching Lee

发明人： Eng Hua Lim ,  Chong Wee Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Pei Ching Lee

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L29/665 ,  H01L21/76232 ,  H01L21/823481

摘要： A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduces contact leakage.

摘要翻译： 描述了形成阶梯式浅沟槽隔离的方法。 衬垫氧化物层沉积在半导体衬底的表面上。 沉积在衬垫氧化物层上的第一氮化物层。 蚀刻第一氮化物层，其中未被掩模覆盖，以提供衬垫氧化物层的开口。 通过开口内的衬垫氧化物层蚀刻第一沟槽并进入半导体衬底。 沉积第二氮化物层，覆盖第一氮化物层并填充第一沟槽。 同时，第二氮化物层被各向异性蚀刻以在第一沟槽的侧壁上形成氮化物间隔物，并且半导体衬底被蚀刻到不被间隔物覆盖的区域中以形成第二沟槽。 离子被注入到第二沟槽下面的半导体衬底中。 第一和第二沟槽填充有氧化物层。 此后，去除在制造集成电路器件时完成形成浅沟槽隔离的第一氮化物层和衬垫氧化物层。 该氮化物间隔物STI结构防止了STI拐角氧化物凹陷并且实现无边界接触形成。 这种独特的工艺可减少结漏电流并减少接触泄漏。

公开(公告)号：US06297126B1

公开(公告)日：2001-10-02

申请号：US09351240

申请日：1999-07-12

申请人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

发明人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/76897

摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.

摘要翻译： 具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。 氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。 形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。 在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。 防止导电钨金属插塞的后续处理被钝化沟槽盖短路。 这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。 此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。 此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

公开(公告)号：US06228727B1

公开(公告)日：2001-05-08

申请号：US09405061

申请日：1999-09-27

申请人： Chong Wee Lim ,  Soh Yun Siah ,  Eng Hua Lim ,  Kong-Hean Lee ,  Chun Hui Low

发明人： Chong Wee Lim ,  Soh Yun Siah ,  Eng Hua Lim ,  Kong-Hean Lee ,  Chun Hui Low

IPC分类号： H01L21336

CPC分类号： H01L21/3086 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/32 ,  H01L21/76232

摘要： A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.

摘要翻译： 已经实现了制造浅沟槽隔离的方法。 提供半导体衬底。 生长覆盖半导体衬底的焊盘氧化物层。 沉积氮化硅层。 将氮化硅层和焊盘氧化物层图案化以形成硬掩模。 硬掩模中的开口对应于半导体衬底中的规划沟槽。 沉积氮化硅层和半导体衬底上的二氧化硅层。 二氧化硅层被各向异性地蚀刻以在硬掩模的开口的内侧上形成侧壁间隔物。 蚀刻半导体衬底以形成沟槽。 蚀刻掉侧壁间隔物。 对半导体衬底进行溅射蚀刻以使沟槽的角落四周。 生长在半导体衬底上的氧化物沟槽衬里层。 沉积氮化硅层并填充沟槽的沟槽填充层。 沟槽填充层被抛光到氮化硅层的顶表面。 蚀刻掉氮化硅层。 沟槽填充层和焊盘氧化物层被抛光到半导体衬底的顶表面以完成浅沟槽隔离，并且集成电路器件完成。

公开(公告)号：US06350661B2

公开(公告)日：2002-02-26

申请号：US09882682

申请日：2001-06-18

申请人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

发明人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/76897

摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.

摘要翻译： 具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。 氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。 形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。 在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。 防止导电钨金属插塞的后续处理被钝化沟槽盖短路。 这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。 此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。 此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

公开(公告)号：US06265302B1

公开(公告)日：2001-07-24

申请号：US09351238

申请日：1999-07-12

申请人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

发明人： Chong Wee Lim ,  Eng Hua Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Chun Hui Low

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76232

摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner. This method of forming borderless contacts with a passivating trench liner in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. In addition, the use of this invention's semi-recessed STI process scheme helps to reduce the aspect ratio of the trench, thereby aiding the filling of the trench. Therefore, with the process described herein, STI oxide seam formation is eliminated.

摘要翻译： 具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽衬垫。 氮化硅钝化衬垫用于形成无边界或“非成形”电触头，而不会减少聚对多晶间距。 形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。 在接触孔开口期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅衬垫保持完好，保护沟槽区域边缘处的P-N结。 防止导电钨金属插塞的后续处理被钝化沟槽衬垫短路。 这种在部分凹槽沟槽隔离方案中与钝化沟槽衬垫形成无边界接触的这种方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。 此外，使用本发明的半凹陷STI工艺方案有助于减小沟槽的纵横比，从而有助于填充沟槽。 因此，通过本文所述的方法，消除了STI氧化物接缝形成。

公开(公告)号：US06271133B1

公开(公告)日：2001-08-07

申请号：US09290918

申请日：1999-04-12

申请人： Chong Wee Lim ,  Eng Hua Lim ,  Kin Leong Pey ,  Soh Yun Siah ,  Chun Hui Low

发明人： Chong Wee Lim ,  Eng Hua Lim ,  Kin Leong Pey ,  Soh Yun Siah ,  Chun Hui Low

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/97

摘要： A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi2 is formed over the source/drain regions by depositing a layer of titanium and annealing this layer with the silicon substrate. The gate electrode is created as a recessed electrode, in the top recession of the electrode a layer of CoSi2 is formed by depositing a layer of cobalt over the gate electrode. This layer of COSi2 serves as the electrical gate contact point.

摘要翻译： 建立了一种新的方法，以在栅电极的顶部和源极/漏极区的表面上形成不同的硅化物层。 通过沉积钛层并用硅衬底退火该层，在源极/漏极区域上形成薄的TiSi 2层。 栅电极被形成为凹陷电极，在电极的顶部凹陷中，通过在栅电极上沉积钴层形成CoSi 2层。 该COSi2层用作电接触点。

公开(公告)号：US06762085B2

公开(公告)日：2004-07-13

申请号：US10262169

申请日：2002-10-01

申请人： Jia Zhen Zheng ,  Soh Yun Siah ,  Liang Choo Hsia ,  Eng Hua Lim ,  Simon Chooi ,  Chew Hoe Ang

发明人： Jia Zhen Zheng ,  Soh Yun Siah ,  Liang Choo Hsia ,  Eng Hua Lim ,  Simon Chooi ,  Chew Hoe Ang

IPC分类号： H01L218238

CPC分类号： H01L29/66598 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

摘要： A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.

摘要翻译： 已经开发了由于光刻掩模程序的减少而制造具有降低的处理成本的CMOS器件的方法。 该方法特征是在栅极结构的侧面上形成L形氧化硅间隔物，其中垂直间隔件部件位于栅极结构的侧面，并且水平间隔件部件位于半导体衬底的表面上，具有厚的水平间隔件 位于邻近门结构的位置，而较薄的水平间隔件组件位于较厚的水平间隔件部件附近。 在CMOS器件的PMOS区域中形成块状形状之后，使用高角度注入工艺在NMOS区域的顶部形成P型卤素区域，随后以较低的注入角度进行另一种注入工艺， 导致在较厚的水平间隔器部件下面的NMOS区域的一部分中的N型LDD区域，并且导致在较薄的水平间隔器部件下面的NMOS的一部分中的N型重掺杂的源极/漏极区域。 执行另一个块状形状，并且进行另一系列相似的注入工艺以在PMOS区域中产生卤素，LDD和源极/漏极区域。 在特定CMOS区域上形成光致抗蚀剂阻挡形状之后，在未被光致抗蚀剂形状覆盖的栅极结构的侧面上形成复合绝缘体间隔物，然后在栅极结构和未被覆盖的源极/漏极区域上形成金属硅化物 光致抗蚀剂阻挡形状。

公开(公告)号：US5956137A

公开(公告)日：1999-09-21

申请号：US186389

申请日：1998-11-05

申请人： Eng Hua Lim ,  Kin-Leong Pey ,  Harianto Wong ,  Kong Hean Lee

发明人： Eng Hua Lim ,  Kin-Leong Pey ,  Harianto Wong ,  Kong Hean Lee

IPC分类号： G01J3/44 ,  H01L21/00

CPC分类号： G01J3/44

摘要： An in-line non-destructive method is described for identifying phases in a micro-structure such as a fine line pattern. This is accomplished by observing the Raman spectrum of the micro-structure. A particular application is a silicide layer, prepared using the SALICIDE process, where the crystal phases before and after Rapid Thermal Anneal are often different. This is reflected by the appearance of different lines in the Raman spectra so that the fraction of each phase can be determined. If the silicide layer agglomerated during the anneal, this is also detected by the Raman spectrum. The method has been used successfully down to line widths of about 0.35 microns.

摘要翻译： 描述了用于识别诸如细线图案的微结构中的相位的在线非破坏性方法。 这是通过观察微结构的拉曼光谱来实现的。 特别的应用是使用SALICIDE工艺制备的硅化物层，其中快速热退火之前和之后的晶相通常是不同的。 这反映在拉曼光谱中不同线的出现，从而可以确定每相的分数。 如果在退火期间硅化物层凝聚，则这也由拉曼光谱检测。 该方法已被成功地应用到约0.35微米的线宽。

公开(公告)号：US08148221B2

公开(公告)日：2012-04-03

申请号：US12581207

申请日：2009-10-19

申请人： Khee Yong Lim ,  Victor Chan ,  Eng Hua Lim ,  Wenhe Lin ,  Jamin F. Fen

发明人： Khee Yong Lim ,  Victor Chan ,  Eng Hua Lim ,  Wenhe Lin ,  Jamin F. Fen

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/3003 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823864 ,  H01L29/7843

摘要： A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

摘要翻译： 使用PFET压缩蚀刻停止衬垫和NFET拉伸蚀刻停止衬垫以及在含氘气氛中的两个退火来形成具有PFET和NFET晶体管的器件的方法。 该方法包括：在PFET区域中的NFET区域中提供NFET晶体管和PFET晶体管。 我们在NFET区域上形成NFET拉伸接触蚀刻停止衬垫。 然后我们进行第一次氘退火。 我们在PFET区域上形成PFET压电蚀刻停止衬垫。 我们在衬底上形成具有接触开口的（ILD）电介质层。 我们进行第二次氘退火。 第二次氘退火的温度小于第一次氘退火的温度。

公开(公告)号：US20080026523A1

公开(公告)日：2008-01-31

申请号：US11495508

申请日：2006-07-28

申请人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan ,  Eng Hua Lim

发明人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan ,  Eng Hua Lim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

摘要： An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.

摘要翻译： 用于制造半导体器件的方法的示例实施例包括以下。 我们提供具有第一器件区域和第二器件区域的衬底。 我们在第一器件区域提供第一类型FET晶体管，并在第二器件区域中提供第二类型FET晶体管。 我们在第一和第二器件区域上形成蚀刻停止层，并在第一器件区域上形成第一应激源层。 第一应力层在第一器件区域中的衬底上施加第一类应力。 我们在第二设备区域上形成第二应力层。 第二应力层在第二器件区域中的衬底上施加第二类应力。 另一示例性实施例是具有蚀刻停止层的双应力层器件的结构。