公开(公告)号：US07256441B2

公开(公告)日：2007-08-14

申请号：US11100500

申请日：2005-04-07

Applicant: Woo-Tag Kang ,  Jungwon Suh

Inventor： Woo-Tag Kang ,  Jungwon Suh

IPC: H01L29/76

CPC classification number: H01L29/66621 ,  H01L27/10876

Abstract: A dynamic random access memory (DRAM) cell structure (and method for making a DRAM cell structure) that is more suitable than current DRAM structures for implementation in ever decreasing semiconductor fabrication geometries. The DRAM cell structure comprises a deep trench (DT) capacitor formed in a substrate. A recess is formed in the substrate proximate the deep trench capacitor. A gate is formed that extends into the recess but does not completely occupy the recess. A source is formed in the substrate in a region beneath the recess. A drain is formed in the substrate in a region laterally and vertically offset from the source. A channel between the source and drain is created beneath the gate along a side wall of the recess. Thus, the depth of the recess determines the length of the channel region. With this DRAM cell structure, it is easier to avoid the high doping concentration issue and the short channel effect. Consequently, this DRAM cell structure can be employed with smaller fabrication technologies.

Abstract translation: 一种动态随机存取存储器（DRAM）单元结构（以及用于制造DRAM单元结构的方法）比当前的DRAM结构更适合于在不断降低的半导体制造几何中实现。 DRAM单元结构包括形成在衬底中的深沟槽（DT）电容器。 在靠近深沟槽电容器的衬底中形成凹部。 形成延伸到凹部中但不完全占据凹部的浇口。 在凹陷下方的区域中的基底中形成源。 在从源极侧向和垂直偏移的区域中在衬底中形成漏极。 源极和漏极之间的通道沿着凹槽的侧壁在栅极下方产生。 因此，凹槽的深度决定了通道区域的长度。 利用这种DRAM单元结构，更容易避免高掺杂浓度问题和短沟道效应。 因此，这种DRAM单元结构可以采用较小的制造技术。

公开(公告)号：US06258645B1

公开(公告)日：2001-07-10

申请号：US09482394

申请日：2000-01-12

Applicant: Woo Tag Kang

Inventor： Woo Tag Kang

IPC: H01L218238

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/10873 ,  H01L27/10894

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract translation: 本发明提供一种CMOS工艺，其中可以制造光晕结构，而不需要使用额外的光刻掩模，用于在光晕植入期间保护相反电导率的晶体管。 晕圈植入物具有位​​于包含相反电导率的晶体管的阱中的LIP注入或反掺杂注入范围内的投影范围或深度。 LIP或反掺杂注入有效地消除了卤素杂质。

公开(公告)号：US6130457A

公开(公告)日：2000-10-10

申请号：US192125

申请日：1998-11-13

Applicant: Sun-il Yu ,  Woo-tag Kang

Inventor： Sun-il Yu ,  Woo-tag Kang

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L29/78603 ,  H01L29/78612 ,  H01L21/76272 ,  H01L21/76281 ,  Y10S438/977

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate. The composite intermediate structure is then inverted and followed by the step of planarizing a second face of the first semiconductor substrate to define a second semiconductor layer. A plurality of spaced semiconductor active regions are then defined in the second semiconductor layer by using field oxide isolation techniques to consume the entire thickness of the second semiconductor layer at predetermined spaced locations. This step essentially isolates the active regions from each other, however, these active regions do not "float" because they are electrically connected to each other indirectly through the underlying first semiconductor layer.

Abstract translation: 形成绝缘体上半导体衬底的方法包括以下步骤：形成下面的半导体层以电连接多个SOI有源区，从而防止一个或多个有源区相对于其它有源区“漂浮”。 浮体效应（FBE）的降低提高了包括SOI MOSFET在内的SOI器件的I-V特性。 提供了一种方法，其包括在第一半导体衬底的第一面上形成其中具有多个第一开口的第二电绝缘层的步骤。 然后在第二电绝缘层上形成第一半导体层，使得在第一半导体层和第一半导体衬底之间形成直接电连接。 然后在第一半导体层上形成第一电绝缘层。 然后将该第一电绝缘层平坦化并结合到第二半导体衬底。 然后将复合中间结构反转，随后平面化第一半导体衬底的第二面以限定第二半导体层的步骤。 然后通过使用场氧化物隔离技术在第二半导体层中限定多个间隔的半导体有源区，以在预定的间隔位置消耗第二半导体层的整个厚度。 该步骤基本上将活性区域彼此隔离，然而，这些活性区域不会“浮动”，因为它们通过下面的第一半导体层间接地彼此电连接。

公开(公告)号：US5877046A

公开(公告)日：1999-03-02

申请号：US835605

申请日：1997-04-09

Applicant: Sun-il Yu ,  Woo-tag Kang

Inventor： Sun-il Yu ,  Woo-tag Kang

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L29/78603 ,  H01L29/78612 ,  H01L21/76272 ,  H01L21/76281 ,  Y10S438/977

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate. The composite intermediate structure is then inverted and followed by the step of planarizing a second face of the first semiconductor substrate to define a second semiconductor layer. A plurality of spaced semiconductor active regions are then defined in the second semiconductor layer by using field oxide isolation techniques to consume the entire thickness of the second semiconductor layer at predetermined spaced locations. This step essentially isolates the active regions from each other, however, these active regions do not "float" because they are electrically connected to each other indirectly through the underlying first semiconductor layer.

Abstract translation: 形成绝缘体上半导体衬底的方法包括以下步骤：形成下面的半导体层以电连接多个SOI有源区，从而防止一个或多个有源区相对于其它有源区“漂浮”。 浮体效应（FBE）的降低提高了包括SOI MOSFET在内的SOI器件的I-V特性。 提供了一种方法，其包括在第一半导体衬底的第一面上形成其中具有多个第一开口的第二电绝缘层的步骤。 然后在第二电绝缘层上形成第一半导体层，使得在第一半导体层和第一半导体衬底之间形成直接电连接。 然后在第一半导体层上形成第一电绝缘层。 然后将该第一电绝缘层平坦化并结合到第二半导体衬底。 然后将复合中间结构反转，随后平面化第一半导体衬底的第二面以限定第二半导体层的步骤。 然后通过使用场氧化物隔离技术在第二半导体层中限定多个间隔的半导体有源区，以在预定的间隔位置消耗第二半导体层的整个厚度。 该步骤基本上将活性区域彼此隔离，然而，这些活性区域不会“浮动”，因为它们通过下面的第一半导体层间接地彼此电连接。

公开(公告)号：US09245881B2

公开(公告)日：2016-01-26

申请号：US12405303

申请日：2009-03-17

Applicant: Woo Tag Kang ,  Jonghae Kim ,  Jungwon Suh

Inventor： Woo Tag Kang ,  Jonghae Kim ,  Jungwon Suh

IPC: H01L49/02 ,  H01L27/08 ,  G06F17/50

CPC classification number: H01L27/0805 ,  G06F17/5068 ,  H01L28/40 ,  Y10T29/49117

Abstract: Methods and devices of a capacitor in a semiconductor device having an increased capacitance are disclosed. In a particular embodiment, a method of forming a capacitor is disclosed. A section of a first insulating material between a first metal contact element and a second metal contact element is removed to form a channel. A second insulating material is deposited in the channel between the first metal contact element and the second metal contact element.

Abstract translation: 公开了具有增加的电容的半导体器件中的电容器的方法和装置。 在特定实施例中，公开了形成电容器的方法。 在第一金属接触元件和第二金属接触元件之间的第一绝缘材料的一部分被去除以形成通道。 在第一金属接触元件和第二金属接触元件之间的通道中沉积第二绝缘材料。

公开(公告)号：US07439591B2

公开(公告)日：2008-10-21

申请号：US10958464

申请日：2004-10-05

Applicant: Woo-Tag Kang

Inventor： Woo-Tag Kang

IPC: H01L23/62 ,  H01L27/14

CPC classification number: G11C11/40626 ,  G11C7/04 ,  G11C11/406 ,  H01L27/0214 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/10897 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/868

Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.

Abstract translation: 用于由集成电路的栅极层的一部分限定的二极管的方法，装置和制造。 提供了本发明的说明性的非限制性实施例，包括温度补偿DRAM，温度补偿CPU，温度补偿逻辑电路和其它片上温度传感器应用。

公开(公告)号：US06930357B2

公开(公告)日：2005-08-16

申请号：US10463023

申请日：2003-06-16

Applicant: Woo-Tag Kang

Inventor： Woo-Tag Kang

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/1087 ,  H01L29/66651

Abstract: A silicon on insulator shaped structure formed to reduce floating body effect comprises a T-shaped active structure and a body contact for back bias. Etching a T-shape through two layers of oxide will form the T-shaped active areas. A back bias is formed when a metal line is dropped through the SOI structure and reaches a contact plug. This contact plug is doped with N+ or P+ dopant and is embedded in a Si substrate. The T-active shaped structure is used to reduce the short channel effects and junction capacitance that normally hinder the effectiveness of bulk transistors. The back bias is used as a conduit for generated holes to leave the SOI transistor area thus greatly reducing the floating effects generally associated with SOI structures.

Abstract translation: 形成为减少浮体效应而形成的绝缘体上的绝缘体结构包括T形有源结构和用于背偏的身体接触。 通过两层氧化物蚀刻T形将形成T形有源区。 当金属线通过SOI结构落下并到达接触塞时，形成背偏压。 该接触插塞掺杂有N +或P +掺杂剂并且嵌入Si衬底中。 T形有源形状结构用于减少通常阻碍体晶体管效率的短沟道效应和结电容。 背偏压用作产生的孔的导管，以离开SOI晶体管区域，从而大大降低了通常与SOI结构相关联的浮动效应。

公开(公告)号：US06724054B1

公开(公告)日：2004-04-20

申请号：US10320867

申请日：2002-12-17

Applicant: Woo-tag Kang ,  Rajeev Malik ,  Mihel Seitz

Inventor： Woo-tag Kang ,  Rajeev Malik ,  Mihel Seitz

IPC: H01L31119

CPC classification number: H01L21/76897 ,  H01L29/6656

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

Abstract translation: 在集成电路中制造自对准接触的方法包括在一对字线堆叠的侧壁上限定第一间隔层。 氧化物层沉积在字线堆叠的顶部上，第一间隔层和设置在第一间隔层之间的衬底的表面。 从第一间隔层去除氧化物层，从而形成覆盖设置在第一间隔层之间的衬底的表面的剩余氧化物层。 第二间隔层形成在第一间隔层之上，并且覆盖剩余氧化物层的各个部分。 除去剩余的氧化物层，从而形成底切区域。 在形成接触期间，底切区域基本上被接触材料填充。

公开(公告)号：US06537885B1

公开(公告)日：2003-03-25

申请号：US10142537

申请日：2002-05-09

Applicant: Woo-Tag Kang ,  Kil-Ho Lee

Inventor： Woo-Tag Kang ,  Kil-Ho Lee

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L29/7834

Abstract: A method of manufacturing a transistor by using two layers of a silicon epitaxial layer is disclosed. In the first step of the manufacturing process, a spacer is formed around gate structures. Then, a first silicon epitaxial layer is grown on the wafer. Then, a second spacer is deposited and then etched, such that the second spacer remains around a gate structure. Next a second silicon epitaxial layer is grown on the first silicon epitaxial layer, and the second spacer is etched from around the gate structure. After etching the first oxide spacer, ions are implanted at a first energy level to form four junctions. Then a third spacer is deposited and etched, so that the third spacer remains around the gate structures. Then ions are implanted at a second energy level to form two more junctions, each of these two junctions being located between two of the earlier formed junctions. The junctions and the gate structures provide a transistor structure. The resulting transistor has a good short channel effect because the junction depths are preferably all aligned. It also has good drive current because the junctions created by ion implantation at a second energy level have low parasitic resistance.

Abstract translation: 公开了通过使用两层硅外延层制造晶体管的方法。 在制造工艺的第一步骤中，在栅极结构周围形成间隔物。 然后，在晶片上生长第一硅外延层。 然后，沉积第二间隔物，然后蚀刻，使得第二间隔物保留在栅极结构周围。 接下来，在第一硅外延层上生长第二硅外延层，并且从栅极结构周围蚀刻第二间隔物。 在蚀刻第一氧化物间隔物之后，以第一能级注入离子以形成四个结。 然后沉积和蚀刻第三间隔物，使得第三间隔物保留在栅极结构周围。 然后离子以第二能级注入以形成两个结，这两个结中的每一个位于两个较早形成的结之间。 结和栅极结构提供晶体管结构。 所得到的晶体管具有良好的短沟道效应，因为结深度优选地全部对准。 它还具有良好的驱动电流，因为在第二能级处由离子注入产生的结具有低寄生电阻。

公开(公告)号：US06218273B1

公开(公告)日：2001-04-17

申请号：US09273868

申请日：1999-03-22

Applicant: Woo-tag Kang

Inventor： Woo-tag Kang

IPC: C30B2518

CPC classification number: H01L21/76224

Abstract: An isolation trench is formed from a first isolation trench in an integrated circuit substrate between active regions in the integrated circuit substrate. An insulating layer is formed in the first isolation trench, wherein the insulating layer includes a portion that protrudes from the first isolation trench. A second isolation trench is formed on the first isolation trench and self-aligned to the active regions in the integrated circuit substrate, wherein the second isolation trench includes the protruding portion of the insulating layer. By forming the isolation trench in two steps, the isolation trench may be formed to the appropriate depth without developing a seam in the insulating layer. In particular, the first isolation trench is formed to a depth and filled with the insulating layer which protrudes from the trench. The second isolation trench is built up around the protruding insulating layer to provide the total depth for adequate isolation of the active areas. The isolation trench may thereby provide improved reliability of the integrated circuit.

Abstract translation: 在集成电路基板中的有源区域之间的集成电路基板中的第一隔离沟槽形成隔离沟槽。 绝缘层形成在第一隔离沟槽中，其中绝缘层包括从第一隔离沟槽突出的部分。 第二隔离沟槽形成在第一隔离沟槽上并与集成电路衬底中的有源区域自对准，其中第二隔离沟槽包括绝缘层的突出部分。 通过在两个步骤中形成隔离沟槽，隔离沟槽可以形成为适当的深度，而不会在绝缘层中形成接缝。 特别地，第一隔离沟槽形成为深度并填充有从沟槽突出的绝缘层。 围绕突出的绝缘层构建第二隔离沟槽，以提供用于充分隔离有源区域的总深度。 因此，隔离沟槽可以提供集成电路的改进的可靠性。