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    Method of fabricating semiconductor device having contact hole with high aspect-ratio
    3.
    发明授权
    Method of fabricating semiconductor device having contact hole with high aspect-ratio 有权
    制造具有高纵横比的接触孔的半导体器件的方法

    公开(公告)号：US07531450B2

    公开(公告)日：2009-05-12

    申请号：US11759788

    申请日：2007-06-07

    Applicant: Yun-Seung Kang ,  Jun Seo ,  Min-Chul Chae ,  Jae-Seung Hwang ,  Sung-Un Kwon ,  Woo-Jin Cho

    Inventor： Yun-Seung Kang ,  Jun Seo ,  Min-Chul Chae ,  Jae-Seung Hwang ,  Sung-Un Kwon ,  Woo-Jin Cho

    IPC: H01L21/44

    CPC classification number: H01L27/11551 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/0688 ,  H01L27/11526

    Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.

    Abstract translation: 提供一种制造具有高纵横比的接触孔的半导体器件的方法。 该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

    ULTRASONIC PROBE
    4.
    发明申请
    ULTRASONIC PROBE 审中-公开
    超声探头

    公开(公告)号：US20150374331A1

    公开(公告)日：2015-12-31

    申请号：US14766684

    申请日：2013-02-07

    Applicant: Woo-jin CHO ,  ALPINION MEDICAL SYSTEMS CO., LTD.

    Inventor： Woo-jin CHO ,  Wonho NOH ,  Sang-woong LEE ,  Sang-seok LEE ,  Jaewon LEE ,  Wonse PARK

    IPC: A61B8/12 ,  A61B8/00

    CPC classification number: A61B8/12 ,  A61B8/4272 ,  A61B8/4444 ,  A61B8/4455 ,  G01N29/226

    Abstract: Embodiments of the present disclosure provide an ultrasonic cavity probe including a grip configured to be held by a user, a lens unit having a predetermined curvature radius, and configured to be inserted into a bodily cavity and to be brought into contact with a skin inside the bodily cavity, a head unit including a first side for mounting the lens unit and rounded corners, and a connecting portion configured to connect the head unit and the grip and to make a first angle with the head unit.

    Abstract translation: 本公开的实施例提供了一种超声波腔探针，其包括构造成由使用者握持的手柄，具有预定曲率半径的镜片单元，并且构造成被插入到体腔中并与内部的皮肤接触 身体腔，包括用于安装透镜单元和圆角的第一侧的头单元和被配置为连接头单元和把手并与头单元形成第一角度的连接部。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING FIN-FET
    5.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING FIN-FET 失效
    制造FIN-FET的半导体器件制造方法

    公开(公告)号：US20080124871A1

    公开(公告)日：2008-05-29

    申请号：US11773372

    申请日：2007-07-03

    Applicant: Jun SEO ,  Jong-Heui SONG ,  Jae-Seung HWANG ,  Min-Chul CHAE ,  Woo-Jin CHO ,  Yun-Seung KANG ,  Young-Mi LEE

    Inventor： Jun SEO ,  Jong-Heui SONG ,  Jae-Seung HWANG ,  Min-Chul CHAE ,  Woo-Jin CHO ,  Yun-Seung KANG ,  Young-Mi LEE

    IPC: H01L21/336

    CPC classification number: H01L29/66795 ,  H01L29/7851

    Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

    Abstract translation: 一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第 牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。 凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

    Methods of fabricating semiconductor device including fin-fet
    6.
    发明授权
    Methods of fabricating semiconductor device including fin-fet 失效
    制造半导体器件的方法包括鳍片

    公开(公告)号：US07745290B2

    公开(公告)日：2010-06-29

    申请号：US11773372

    申请日：2007-07-03

    Applicant: Jun Seo ,  Jong-Heui Song ,  Jae-Seung Hwang ,  Min-Chul Chae ,  Woo-Jin Cho ,  Yun-Seung Kang ,  Young-Mi Lee

    Inventor： Jun Seo ,  Jong-Heui Song ,  Jae-Seung Hwang ,  Min-Chul Chae ,  Woo-Jin Cho ,  Yun-Seung Kang ,  Young-Mi Lee

    IPC: H01L21/336

    CPC classification number: H01L29/66795 ,  H01L29/7851

    Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

    Abstract translation: 一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第 牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。 凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

    Exposure Mask for Forming Photodiode and Method of Manufacturing Image Sensor Using the Same
    7.
    发明申请
    Exposure Mask for Forming Photodiode and Method of Manufacturing Image Sensor Using the Same 审中-公开
    用于形成光电二极管的曝光掩模和使用其的图像传感器的制造方法

    公开(公告)号：US20100092875A1

    公开(公告)日：2010-04-15

    申请号：US12562691

    申请日：2009-09-18

    Applicant: Woo Jin Cho

    Inventor： Woo Jin Cho

    IPC: G03F1/00 ,  G03F7/20

    CPC classification number: H01L27/14689 ,  G03F1/36 ,  H01L27/14607

    Abstract: An exposure mask for forming a photodiode of an image sensor and a method of manufacturing an image sensor using the exposure mask may be disclosed. An exposure mask for forming a photodiode of an image sensor includes a plurality of main open patterns, each having a first open pattern that is rectangular and a second open pattern extending outward from at least one corner of the first open pattern, and an open serif extending outward from each of the corners of the second open pattern that do not overlap with the first open pattern, covering a predetermined area adjacent to the second open pattern.

    Abstract translation: 可以公开用于形成图像传感器的光电二极管的曝光掩模和使用该曝光掩模的图像传感器的制造方法。 用于形成图像传感器的光电二极管的曝光掩模包括多个主开口图案，每个主开放图案具有矩形的第一开放图案和从第一开放图案的至少一个角向外延伸的第二开放图案，以及开放衬线 从与第一开放图案不重叠的第二开放图案的每个角落向外延伸，覆盖与第二打开图案相邻的预定区域。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20090020816A1

    公开(公告)日：2009-01-22

    申请号：US12175364

    申请日：2008-07-17

    Applicant: Woo-Jin CHO ,  Yong-Woo LEE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Min-Chul CHAE

    Inventor： Woo-Jin CHO ,  Yong-Woo LEE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Min-Chul CHAE

    IPC: H01L29/00

    CPC classification number: H01L27/0688 ,  H01L21/8221

    Abstract: One embodiment generally described herein can be characterized as a semiconductor device. The semiconductor device can include a first transistor on a semiconductor substrate. A first interlayer insulating layer may be disposed over the first transistor and includes a first recess region. A single-crystalline semiconductor pattern may be disposed in the first recess region. A single-crystalline semiconductor plug may connect the semiconductor substrate to the single-crystalline semiconductor pattern. A second transistor may be disposed on the single-crystalline semiconductor pattern.

    Abstract translation: 本文通常描述的一个实施例可以被表征为半导体器件。 半导体器件可以包括半导体衬底上的第一晶体管。 第一层间绝缘层可以设置在第一晶体管的上方，并且包括第一凹部区域。 单晶半导体图案可以设置在第一凹部区域中。 单晶半导体插头可以将半导体衬底连接到单晶半导体图案。 第二晶体管可以设置在单晶半导体图案上。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CONTACT HOLE WITH HIGH ASPECT-RATIO
    9.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CONTACT HOLE WITH HIGH ASPECT-RATIO 有权
    具有高比例比例接触孔的半导体器件的制造方法

    公开(公告)号：US20070287287A1

    公开(公告)日：2007-12-13

    申请号：US11759788

    申请日：2007-06-07

    Applicant: Yun-Seung KANG ,  Jun SEO ,  Min-Chul CHAE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Woo-Jin CHO

    Inventor： Yun-Seung KANG ,  Jun SEO ,  Min-Chul CHAE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Woo-Jin CHO

    IPC: H01L21/44

    CPC classification number: H01L27/11551 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/0688 ,  H01L27/11526

    Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.

    Abstract translation: 提供一种制造具有高纵横比的接触孔的半导体器件的方法。 该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

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