公开(公告)号：US20110109354A1

公开(公告)日：2011-05-12

申请号：US12902773

申请日：2010-10-12

申请人： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

发明人： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

IPC分类号： H03L7/06

CPC分类号： H03K5/156

摘要： In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

摘要翻译： 通常，本公开涉及一种调整时钟信号的下降沿以实现期望的占空比的占空比校正（DCC）电路。 在一些示例中，DCC电路可以响应于输入时钟信号的下降沿产生脉冲，基于控制电压延迟脉冲，基于延迟的脉冲调整输入时钟信号的下降沿以产生输出 时钟信号，并且基于输出时钟信号的占空比与期望的占空比之间的差来调节控制电压。 由于DCC电路调整时钟周期的下降沿以实现期望的占空比，所以DCC可以被并入现有的PLL控制环路中，该PLL控制环路调整时钟信号的上升沿，而不会干扰这种PLL控制环路的操作。

公开(公告)号：US07839195B1

公开(公告)日：2010-11-23

申请号：US12455572

申请日：2009-06-03

申请人： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

发明人： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

IPC分类号： H03K5/04 ,  H03L7/06

CPC分类号： H03K5/156

摘要： In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

摘要翻译： 通常，本公开涉及一种调整时钟信号的下降沿以实现期望的占空比的占空比校正（DCC）电路。 在一些示例中，DCC电路可以响应于输入时钟信号的下降沿产生脉冲，基于控制电压延迟脉冲，基于延迟的脉冲调整输入时钟信号的下降沿以产生输出 时钟信号，并且基于输出时钟信号的占空比与期望的占空比之间的差来调节控制电压。 由于DCC电路调整时钟周期的下降沿以实现期望的占空比，所以DCC可以被并入现有的PLL控制环路中，该PLL控制环路调整时钟信号的上升沿，而不会干扰这种PLL控制环路的操作。

公开(公告)号：US08093956B2

公开(公告)日：2012-01-10

申请号：US12352100

申请日：2009-01-12

申请人： Xiaoxin Feng ,  Jeffrey Loukusa

发明人： Xiaoxin Feng ,  Jeffrey Loukusa

IPC分类号： H03L1/02

CPC分类号： G05F1/575 ,  G05F3/30

摘要： A temperature-compensated-resistance (TCR) circuit, which may be part of an integrated circuit, is provided. The TCR circuit consists of two resistors and a diode. The two resistors are connected in parallel and the diode is connected in series with one of the resistors. The two parallel legs of the TCR circuit may be connected to a reference voltage source, such as a ground. No specialized devices, such as bipolar transistors, Zener or Schottky diodes, or specially-processed resistors, are required by the TCR circuit. The resistors and the diode of the TCR circuit may be chosen to adjust for temperature variations in the resistance values of the resistor, leading to a negative, zero, or positive temperature coefficient of resistance for the circuit. A phase-locked loop (PLL) circuit is described as an application of the TCR circuit.

摘要翻译： 提供可以是集成电路的一部分的温度补偿电阻（TCR）电路。 TCR电路由两个电阻和一个二极管组成。 两个电阻并联连接，二极管与电阻之一串联连接。 TCR电路的两个平行支路可以连接到参考电压源，例如地面。 TCR电路不需要专门的器件，例如双极晶体管，齐纳二极管或肖特基二极管，或特殊处理的电阻器。 可以选择TCR电路的电阻器和二极管来调节电阻器的电阻值的温度变化，导致电路的负，零或正温度系数。 锁相环（PLL）电路被描述为TCR电路的应用。

公开(公告)号：US20100176886A1

公开(公告)日：2010-07-15

申请号：US12352100

申请日：2009-01-12

申请人： Xiaoxin Feng ,  Jeffrey Loukusa

发明人： Xiaoxin Feng ,  Jeffrey Loukusa

IPC分类号： H03L7/00 ,  G01K7/00

CPC分类号： G05F1/575 ,  G05F3/30

摘要： A temperature-compensated-resistance (TCR) circuit, which may be part of an integrated circuit, is provided. The TCR circuit consists of two resistors and a diode. The two resistors are connected in parallel and the diode is connected in series with one of the resistors. The two parallel legs of the TCR circuit may be connected to a reference voltage source, such as a ground. No specialized devices, such as bipolar transistors, Zener or Schottky diodes, or specially-processed resistors, are required by the TCR circuit. The resistors and the diode of the TCR circuit may be chosen to adjust for temperature variations in the resistance values of the resistor, leading to a negative, zero, or positive temperature coefficient of resistance for the circuit. A phase-locked loop (PLL) circuit is described as an application of the TCR circuit.

摘要翻译： 提供可以是集成电路的一部分的温度补偿电阻（TCR）电路。 TCR电路由两个电阻和一个二极管组成。 两个电阻并联连接，二极管与电阻之一串联连接。 TCR电路的两个平行支路可以连接到参考电压源，例如地面。 TCR电路不需要专门的器件，例如双极晶体管，齐纳二极管或肖特基二极管，或特殊处理的电阻器。 可以选择TCR电路的电阻器和二极管来调节电阻器的电阻值的温度变化，导致电路的负，零或正温度系数。 锁相环（PLL）电路被描述为TCR电路的应用。

公开(公告)号：US08390352B2

公开(公告)日：2013-03-05

申请号：US12418981

申请日：2009-04-06

申请人： James Seefeldt ,  Xiaoxin Feng ,  Weston Roper

发明人： James Seefeldt ,  Xiaoxin Feng ,  Weston Roper

IPC分类号： H03L7/00

CPC分类号： G11C29/022 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K2005/00097 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

摘要翻译： 提供过程，电压和温度（PVT）补偿电路以及连续生成延迟测量的方法。 补偿电路包括两个延迟线，每个延迟线提供延迟输出。 两个延迟线可以各自包括多个延迟元件，延迟元件又包括一个或多个当前饥饿的逆变器。 延迟线的数量可能在两个延迟线之间不同。 延迟输出被提供给组合电路，该组合电路基于两个延迟输出确定偏移脉冲，然后平均偏移脉冲的电压以确定延迟测量。 延迟测量可以是指示应用于应用电路的输入或输出信号的PVT补偿量的一个或多个电流或电压，诸如存储器总线驱动器，动态随机存取存储器（DRAM），同步DRAM， 处理器或其他时钟电路。

公开(公告)号：US20100308878A1

公开(公告)日：2010-12-09

申请号：US12455572

申请日：2009-06-03

申请人： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

发明人： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

IPC分类号： H03L7/06 ,  H03K5/04

CPC分类号： H03K5/156

摘要： In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

摘要翻译： 通常，本公开涉及一种调整时钟信号的下降沿以实现期望的占空比的占空比校正（DCC）电路。 在一些示例中，DCC电路可以响应于输入时钟信号的下降沿产生脉冲，基于控制电压延迟脉冲，基于延迟的脉冲调整输入时钟信号的下降沿以产生输出 时钟信号，并且基于输出时钟信号的占空比与期望的占空比之间的差来调节控制电压。 由于DCC电路调整时钟周期的下降沿以实现期望的占空比，所以DCC可以被并入现有的PLL控制环路中，该PLL控制环路调整时钟信号的上升沿，而不会干扰这种PLL控制环路的操作。

公开(公告)号：US06900663B1

公开(公告)日：2005-05-31

申请号：US10288003

申请日：2002-11-04

申请人： Weston Roper ,  Xiaoxin Feng

发明人： Weston Roper ,  Xiaoxin Feng

IPC分类号： H03K19/094

CPC分类号： H04L25/028

摘要： Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's output, an electronic load circuit coupled across the circuit, and a common-mode resistor feedback circuit coupled across the circuit, in parallel with the RC load, for tuning the driver's impedance. The driver is enabled to operate without op-amps and achieves optimum performance at 1.8 v supply voltages.

摘要翻译： 本发明的实施例涉及一种低电压差分信号驱动器（LVDS）电路，其包括电流源，用于控制驱动器输出的逻辑控制开关，耦合在电路两端的电子负载电路和耦合到共模电阻器反馈电路 跨过电路，与RC负载并联，用于调整驱动器的阻抗。 驱动器能够在没有运算放大器的情况下运行，并在1.8 V电源电压下实现最佳性能。

公开(公告)号：US6021162A

公开(公告)日：2000-02-01

申请号：US941949

申请日：1997-10-01

申请人： Michael Gaboury ,  Xiaoxin Feng

发明人： Michael Gaboury ,  Xiaoxin Feng

IPC分类号： H04L27/156 ,  H04B14/04

CPC分类号： H04L27/1563

摘要： A method of and apparatus for decoding an encoded signal are disclosed. A first bit of the encoded signal is received and integrated with a super linear integrator to provide a first integration signal. A first reference signal is provided as a function of a previous integration signal associated with a previous bit of the encoded signal by multiplying the previous integration signal by an amount greater than one if the previous bit has a first value, and by multiplying the previous integration signal by an amount less than one if the previous bit has a second value. The first integration signal is compared to the first reference signal and a first bit of an output signal is provided based upon the comparison. The first bit of the output signal is indicative of information encoded in the first bit of the encoded signal.

摘要翻译： 公开了一种用于对编码信号进行解码的方法和装置。 编码信号的第一位被接收并与超线性积分器集成以提供第一积分信号。 如果先前的位具有第一值，则通过将先前的积分信号乘以大于1的量，并且通过将先前的积分信号乘以前一积分信号，将第一参考信号作为与编码信号的先前位相关联的先前积分信号的函数， 如果前一位具有第二值，则信号的量小于1。 将第一积分信号与第一参考信号进行比较，并且基于比较提供输出信号的第一位。 输出信号的第一位表示编码在编码信号的第一位中的信息。

公开(公告)号：US20100253406A1

公开(公告)日：2010-10-07

申请号：US12418981

申请日：2009-04-06

申请人： James Seefeldt ,  Xiaoxin Feng ,  Weston Roper

发明人： James Seefeldt ,  Xiaoxin Feng ,  Weston Roper

IPC分类号： H03L1/00 ,  H03L7/00 ,  G01R25/00

CPC分类号： G11C29/022 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K2005/00097 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

摘要翻译： 提供过程，电压和温度（PVT）补偿电路以及连续生成延迟测量的方法。 补偿电路包括两个延迟线，每个延迟线提供延迟输出。 两个延迟线可以各自包括多个延迟元件，延迟元件又包括一个或多个当前饥饿的逆变器。 延迟线的数量可能在两个延迟线之间不同。 延迟输出被提供给组合电路，该组合电路基于两个延迟输出确定偏移脉冲，然后平均偏移脉冲的电压以确定延迟测量。 延迟测量可以是指示应用于应用电路的输入或输出信号的PVT补偿量的一个或多个电流或电压，诸如存储器总线驱动器，动态随机存取存储器（DRAM），同步DRAM， 处理器或其他时钟电路。