公开(公告)号：US08451062B2

公开(公告)日：2013-05-28

申请号：US13190285

申请日：2011-07-25

Applicant: James D. Seefeldt ,  Keith Golke

Inventor： James D. Seefeldt ,  Keith Golke

IPC: H03F3/68

CPC classification number: H03F3/45183 ,  H03F3/211 ,  H03F2203/45352 ,  H03F2203/45366 ,  H03F2203/45674

Abstract: This disclosure is directed to techniques for preventing or reducing perturbations of an output signal of a differential amplifier caused by ionizing radiation incident upon the amplifier. The amplifier may include an amplification module that includes a plurality of amplification units configured to amplify a difference between a first component and a second component of a differential voltage signal to generate a plurality of amplified difference signals each corresponding to the amplified difference. The amplifier may further include a combination module that combines the plurality of amplified difference signals to generate a common output signal corresponding to the amplified difference.

Abstract translation: 本公开涉及用于防止或减少由入射在放大器上的电离辐射引起的差分放大器的输出信号的扰动的技术。 放大器可以包括放大模块，其包括多个放大单元，其被配置为放大差分电压信号的第一分量和第二分量之间的差，以产生每个对应于放大差值的多个放大差分信号。 放大器还可以包括组合多个放大的差分信号以产生对应于放大差分的公共输出信号的组合模块。

公开(公告)号：US20110109354A1

公开(公告)日：2011-05-12

申请号：US12902773

申请日：2010-10-12

Applicant: Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

Inventor： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

IPC: H03L7/06

CPC classification number: H03K5/156

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract translation: 通常，本公开涉及一种调整时钟信号的下降沿以实现期望的占空比的占空比校正（DCC）电路。 在一些示例中，DCC电路可以响应于输入时钟信号的下降沿产生脉冲，基于控制电压延迟脉冲，基于延迟的脉冲调整输入时钟信号的下降沿以产生输出 时钟信号，并且基于输出时钟信号的占空比与期望的占空比之间的差来调节控制电压。 由于DCC电路调整时钟周期的下降沿以实现期望的占空比，所以DCC可以被并入现有的PLL控制环路中，该PLL控制环路调整时钟信号的上升沿，而不会干扰这种PLL控制环路的操作。

公开(公告)号：US07839195B1

公开(公告)日：2010-11-23

申请号：US12455572

申请日：2009-06-03

Applicant: Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

Inventor： Xiaoxin Feng ,  Weston Roper ,  James D. Seefeldt

IPC: H03K5/04 ,  H03L7/06

CPC classification number: H03K5/156

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract translation: 通常，本公开涉及一种调整时钟信号的下降沿以实现期望的占空比的占空比校正（DCC）电路。 在一些示例中，DCC电路可以响应于输入时钟信号的下降沿产生脉冲，基于控制电压延迟脉冲，基于延迟的脉冲调整输入时钟信号的下降沿以产生输出 时钟信号，并且基于输出时钟信号的占空比与期望的占空比之间的差来调节控制电压。 由于DCC电路调整时钟周期的下降沿以实现期望的占空比，所以DCC可以被并入现有的PLL控制环路中，该PLL控制环路调整时钟信号的上升沿，而不会干扰这种PLL控制环路的操作。

公开(公告)号：US07718963B2

公开(公告)日：2010-05-18

申请号：US11841432

申请日：2007-08-20

Applicant: James D. Seefeldt ,  Jeffrey J. Kriz

Inventor： James D. Seefeldt ,  Jeffrey J. Kriz

IPC: G01T1/00

CPC classification number: G01T1/026 ,  H01L31/117

Abstract: A radiation sensor and a method for making the radiation sensor are described. An ionizing radiation sensitive area is formed in a radiation insensitive or hardened die. When the sensitive area is impacted by ionizing radiation, properties of the sensitive area change. For example, the changed property may be charge density, threshold voltage, leakage current, and/or resistance. Circuitry for measuring these property changes is located in a radiation hardened area of the die. As a result, a radiation sensor may be fabricated on a single die.

Abstract translation: 描述辐射传感器和制造辐射传感器的方法。 在辐射不敏感或硬化的模具中形成电离辐射敏感区域。 当敏感区域受到电离辐射的影响时，敏感区域的性质发生变化。 例如，改变的特性可以是电荷密度，阈值电压，漏电流和/或电阻。 用于测量这些性能变化的电路位于模具的辐射硬化区域中。 结果，可以在单个管芯上制造辐射传感器。

公开(公告)号：US07323946B2

公开(公告)日：2008-01-29

申请号：US11254569

申请日：2005-10-20

Applicant: James D. Seefeldt ,  Bradley A. Kantor

Inventor： James D. Seefeldt ,  Bradley A. Kantor

IPC: H03L7/085 ,  H03L7/08

CPC classification number: H03D13/004 ,  H03L7/095 ,  Y10S331/02

Abstract: An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.

Abstract translation: 描述了用于确定锁相环（PLL）的锁定状态的改进的系统和方法。 锁定检测电路产生快速锁定检测信号，其可用于检测瞬时的锁定损失。 锁定检测电路还可以包括相位对准检测电路，用于检测参考时钟和反馈时钟的相位中的未对准。 此外，锁定检测电路可以包括参考时钟检测电路，以检测是否检测到参考时钟信号。 来自所有上述电路的输出信号可以被传送到逻辑电路，以便产生增强的锁定检测信号。 扩展锁定检测信号也可以被传送到逻辑电路。

公开(公告)号：US07283010B2

公开(公告)日：2007-10-16

申请号：US11254473

申请日：2005-10-20

Applicant: James D. Seefeldt

Inventor： James D. Seefeldt

IPC: H03L7/099

CPC classification number: H03K5/133 ,  H03K2005/0013 ,  H03L7/0995

Abstract: An apparatus and method for providing a power supply compensated voltage or current is presented. A supply compensated current and voltage source utilizes a differential amplifier connected to a bandgap reference voltage and a scaled power supply voltage. When power supply varies, the differential amplifier regulates a stable compensated output. The output may be a compensated voltage or current. In addition, multiple currents and voltages may be referenced from the differential amplifier. The stable compensated output may be supplied as a reference bias for external circuitry. In addition, the compensated output may be supplied to a voltage controlled oscillator.

Abstract translation: 提出了一种用于提供电源补偿电压或电流的装置和方法。 电源补偿电流和电压源使用连接到带隙参考电压和缩放电源电压的差分放大器。 当电源变化时，差分放大器调节稳定的补偿输出。 输出可以是补偿电压或电流。 此外，可以从差分放大器参考多个电流和电压。 稳定的补偿输出可以作为外部电路的参考偏置来提供。 此外，补偿输出可以被提供给压控振荡器。

公开(公告)号：US5796291A

公开(公告)日：1998-08-18

申请号：US619166

申请日：1996-03-21

Applicant: Michael F. Mattes ,  James D. Seefeldt

Inventor： Michael F. Mattes ,  James D. Seefeldt

IPC: G01D3/028 ,  G01D5/14 ,  G01L1/22 ,  G01L9/06 ,  H03F1/30 ,  H03G1/04 ,  H01L35/00

CPC classification number: H03G1/04 ,  G01L1/2281 ,  G01L9/065 ,  H03F1/30

Abstract: An electronic gain circuit adapted to receive an input signal, an amplifier having a gain for amplifying the input signal to produce an output signal, and biasing resistors connected to the amplifier to automatically adjust the gain of the amplifier in response to fluctuations in ambient temperature such that the output signal of the amplifier responds to ambient temperature fluctuations.

Abstract translation: 一种适于接收输入信号的电子增益电路，具有用于放大输入信号以产生输出信号的增益的放大器，以及连接到放大器的偏置电阻器，以响应于环境温度的波动自动调节放大器的增益， 放大器的输出信号响应于环境温度波动。

公开(公告)号：US5708190A

公开(公告)日：1998-01-13

申请号：US624668

申请日：1996-04-02

Applicant: James D. Seefeldt ,  Michael F. Mattes

Inventor： James D. Seefeldt ,  Michael F. Mattes

IPC: G01N7/00 ,  G01L19/12 ,  G01N33/00

CPC classification number: G01N33/0062 ,  G01L19/12

Abstract: A gas concentration sensor for use in a closed container having a constant volume and gas within the container, wherein the gas has a known pressure at a given temperature. The sensor includes a pressure sensing device disposed within the container, wherein the pressure sensing device generates a first electrical signal functionally related to the gas pressure within the container. The sensor also includes an electronic circuit connected to the pressure sensing device which amplifies the first electrical signal and produces a second electrical signal functionally related to the gas concentration within the volume at any temperature.

Abstract translation: 一种气体浓度传感器，用于在容器内具有恒定体积和气体的密闭容器中，其中气体在给定温度下具有已知的压力。 传感器包括设置在容器内的压力感测装置，其中压力感测装置产生与容器内的气体压力功能相关的第一电信号。 传感器还包括连接到压力感测装置的电子电路，其放大第一电信号并且产生与任何温度下的体积内的气体浓度功能相关的第二电信号。

公开(公告)号：US08058689B2

公开(公告)日：2011-11-15

申请号：US12939770

申请日：2010-11-04

Applicant: Cheisan J. Yue ,  James D. Seefeldt

Inventor： Cheisan J. Yue ,  James D. Seefeldt

IPC: H01L29/786

CPC classification number: H01L21/76283 ,  H01L21/765 ,  H01L21/84 ,  H01L27/1203

Abstract: An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.

Abstract translation: 集成电路具有形成在半导体衬底上的掩埋绝缘层和形成在掩埋绝缘层上的半导体台面。 低电阻率保护环基本上围绕半导体台面并与半导体衬底接触。 低电阻率保护环接地，并将半导体台面与RF信号隔离开来。

公开(公告)号：US07423492B2

公开(公告)日：2008-09-09

申请号：US11254474

申请日：2005-10-20

Applicant: James D. Seefeldt

Inventor： James D. Seefeldt

IPC: H03L7/095

CPC classification number: H03L7/105 ,  H03L7/095 ,  H03L7/10 ,  Y10S331/02

Abstract: A system and method for generating a reset signal within a Phase Locked Loop (PLL) circuit is described. The reset signal is generated by inputting a reference signal and a lock detect signal into reset circuitry. The reset circuitry within the PLL comprises a series of interconnected latches, or D flip-flops, which are used to create a delay time. The delay time is the amount of time the reset circuit will wait until the reset signal indicates a reset. The reset circuit may also generate a reset signal having a pulse width. The pulse width is determined by the series of interconnected latches. The reset signal may be used to reset a Voltage Controlled Oscillator (VCO) or other circuits within a PLL or it may be used by circuits external to the PLL.

Abstract translation: 描述了在锁相环（PLL）电路内产生复位信号的系统和方法。 通过将参考信号和锁定检测信号输入复位电路来产生复位信号。 PLL内的复位电路包括一系列互连的锁存器或D触发器，用于产生延迟时间。 延迟时间是复位电路等待复位信号指示复位的时间量。 复位电路还可以产生具有脉冲宽度的复位信号。 脉冲宽度由一系列互连的锁存器确定。 复位信号可用于复位压控振荡器（VCO）或PLL内的其他电路，或者可由PLL外部的电路使用复位信号。