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    Method of fabrication of heterogeneous integrated circuits and devices thereof
    1.
    发明授权
    Method of fabrication of heterogeneous integrated circuits and devices thereof 有权
    异质集成电路的制造方法及其装置

    公开(公告)号：US07972936B1

    公开(公告)日：2011-07-05

    申请号：US12365112

    申请日：2009-02-03

    Applicant: Peter D. Brewer ,  Andrew T. Hunter ,  Yakov Royter

    Inventor： Peter D. Brewer ,  Andrew T. Hunter ,  Yakov Royter

    IPC: H01L21/30

    CPC classification number: H01L21/185 ,  H01L21/18 ,  H01L21/187 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/82 ,  H01L21/8258

    Abstract: A heterogeneous integrated circuit and method of making the same. An integrated circuit includes a surrogate substrate including a material selected from the group consisting of Group II, Group III, Group IV, Group V, and Group VI materials and their combinations; at least one active semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials; and at least one transferred semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials. The at least one active semiconductor device and the at least one transferred device are interconnected.

    Abstract translation: 异构集成电路及其制作方法。 集成电路包括包括选自由组II，组III，组IV，组V和组VI材料及其组合组成的组的材料的替代衬底; 至少一个活性半导体器件，其包括选自由IV-IV族，III-V族和II-VI族组成的组的材料组合; 以及至少一个转移的半导体器件，其包括选自由IV-IV族，III-V族和II-VI族组成的组的材料组合。 所述至少一个有源半导体器件和所述至少一个转移器件互连。

    Thermal management substrate
    2.
    发明授权
    Thermal management substrate 有权
    热管理基板

    公开(公告)号：US07695564B1

    公开(公告)日：2010-04-13

    申请号：US11051749

    申请日：2005-02-03

    Applicant: Miroslav Micovic ,  Peter Deelman ,  Yakov Royter

    Inventor： Miroslav Micovic ,  Peter Deelman ,  Yakov Royter

    IPC: C30B25/02

    CPC classification number: H01L21/76254

    Abstract: The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.

    Abstract translation: 本发明涉及一种用于制造在多晶金刚石膜上或在金刚石碳（DLC）膜上具有硅（Si）层的热管理基板的方法。 该方法包括通过注入氧（SIMOX）晶片制造分离的作用; 将多晶金刚石膜沉积到SIMOX晶片上; 并移除SIMOX晶片的各层以留下与多晶金刚石膜外延熔合的Si覆盖层。 在DLC膜的情况下，该方法包括离子注入Si晶片的动作; 在Si晶片上沉积非晶态DLC膜; 并去除Si晶片的各个层以留下与DLC膜外延融合的Si覆盖结构。

    Implantation before epitaxial growth for photonic integrated circuits
    5.
    发明授权
    Implantation before epitaxial growth for photonic integrated circuits 有权
    光子集成电路外延生长之前的植入

    公开(公告)号：US08900896B1

    公开(公告)日：2014-12-02

    申请号：US13030094

    申请日：2011-02-17

    Applicant: Yakov Royter ,  Rajesh D. Rajavel ,  Irina Ionova ,  Sophi Ionova

    Inventor： Yakov Royter ,  Rajesh D. Rajavel ,  Stanislav I. Ionov

    IPC: H01L21/00

    CPC classification number: G02B6/13 ,  B82Y20/00 ,  G02F1/01708 ,  G02F2201/063 ,  G02F2202/06 ,  G02F2202/102 ,  H01L21/2654 ,  H01S5/026

    Abstract: Fabrication of a photonic integrated circuit (PIC) including active elements such as a semiconductor optical amplifier (SOA) and passive elements such as a floating rib waveguide. Selective area doping through ion implantation or thermal diffusion before semiconductor epitaxial growth is used in order to define the contact and lateral current transport layers for each active device, while leaving areas corresponding to the passive devices undoped. InP wafers are used as the substrate which may be selectively doped with silicon.

    Abstract translation: 包括诸如半导体光放大器（SOA）和无源元件（诸如浮动肋波导）的有源元件的光子集成电路（PIC）的制造。 使用在半导体外延生长之前通过离子注入或热扩散的选择性区域掺杂以便限定每个有源器件的接触和横向电流传输层，同时留下对应于被动器件未被掺杂的区域。 InP晶片用作可选择性掺杂硅的衬底。

    Heterogeneous integrated circuits and devices thereof with a surrogate substrate and transferred semiconductor devices
    7.
    发明授权
    Heterogeneous integrated circuits and devices thereof with a surrogate substrate and transferred semiconductor devices 有权
    异质集成电路及其装置具有替代衬底和转移的半导体器件

    公开(公告)号：US09524872B1

    公开(公告)日：2016-12-20

    申请号：US13096780

    申请日：2011-04-28

    Applicant: Peter D. Brewer ,  Andrew T. Hunter ,  Yakov Royter

    Inventor： Peter D. Brewer ,  Andrew T. Hunter ,  Yakov Royter

    IPC: H01L21/30 ,  H01L21/18

    CPC classification number: H01L21/185 ,  H01L21/18 ,  H01L21/187 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/82 ,  H01L21/8258

    Abstract: A heterogeneous integrated circuit and method of making the same. An integrated circuit includes a surrogate substrate including a material selected from the group consisting of Group II, Group III, Group IV, Group V, and Group VI materials and their combinations; at least one active semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials; and at least one transferred semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials. The at least one active semiconductor device and the at least one transferred device are interconnected.

    Abstract translation: 异构集成电路及其制作方法。 集成电路包括包括选自由组II，组III，组IV，组V和组VI材料及其组合组成的组的材料的替代衬底; 至少一个活性半导体器件，其包括选自由IV-IV族，III-V族和II-VI族组成的组的材料组合; 以及至少一个转移的半导体器件，其包括选自由IV-IV族，III-V族和II-VI族组成的组的材料组合。 所述至少一个有源半导体器件和所述至少一个转移器件互连。

    Bipolar transistors with low parasitic losses
    8.
    发明授权
    Bipolar transistors with low parasitic losses 失效
    具有低寄生损耗的双极晶体管

    公开(公告)号：US07368765B1

    公开(公告)日：2008-05-06

    申请号：US11313862

    申请日：2005-12-20

    Applicant: Rajesh D. Rajavel ,  David H. Chow ,  Tahir Hussain ,  Yakov Royter

    Inventor： Rajesh D. Rajavel ,  David H. Chow ,  Tahir Hussain ,  Yakov Royter

    IPC: H01L29/739 ,  H01L31/00

    CPC classification number: H01L29/732 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

    Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

    Abstract translation: 提出了双极结晶体管（BJT）和具有低寄生效应的单或双异质结双极晶体管及其制造方法。 制造晶体管使得基极接触区域下面的集电极区域被去激活。 这导致基极 - 集电极寄生电容C bc 的急剧减小。 本发明的一个实施例提供一种晶体管架构，其基极接触区域可以与集电极分离，因此允许显着降低晶体管的寄生效应。

    Memristor devices and fabrication
    9.
    发明授权
    Memristor devices and fabrication 有权
    忆阻器的装置和制造

    公开(公告)号：US09450022B1

    公开(公告)日：2016-09-20

    申请号：US13604559

    申请日：2012-09-05

    Applicant: Dana C. Wheeler ,  Tahir Hussain ,  Yakov Royter ,  Eason F. Wang

    Inventor： Dana C. Wheeler ,  Tahir Hussain ,  Yakov Royter ,  Eason F. Wang

    IPC: H01L27/24 ,  H01L21/00

    CPC classification number: H01L27/2418 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

    Abstract: A method for fabricating a digital memristor crossbar array includes applying a protective layer on at least a portion of a memristive layer. A method for fabricating an analog memristor crossbar array includes providing a self-aligning first electrode layer. An analog memristor includes a memristive layer bar arranged to self-align said second electrode on said memristive layer along its length.

    Abstract translation: 数字忆阻器横杆阵列的制造方法包括在至少一部分忆阻层上施加保护层。 一种用于制造模拟忆阻器交叉开关阵列的方法包括提供自对准的第一电极层。 模拟忆阻器包括设置成沿其长度自对准所述忆阻层上的所述第二电极的忆阻层条。

    Bipolar transistors with low parasitic losses
    10.
    发明授权
    Bipolar transistors with low parasitic losses 失效
    具有低寄生损耗的双极晶体管

    公开(公告)号：US07569872B1

    公开(公告)日：2009-08-04

    申请号：US11313865

    申请日：2005-12-20

    Applicant: Rajesh D. Rajavel ,  David H. Chow ,  Tahir Hussain ,  Yakov Royter

    Inventor： Rajesh D. Rajavel ,  David H. Chow ,  Tahir Hussain ,  Yakov Royter

    IPC: H01L29/739 ,  H01L31/072

    CPC classification number: H01L29/7371 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66318

    Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

    Abstract translation: 提出了双极结晶体管（BJT）和具有低寄生效应的单或双异质结双极晶体管及其制造方法。 制造晶体管使得基极接触区域下面的集电极区域被去激活。 这导致基极集电极寄生电容Cbc的急剧减小。 本发明的一个实施例提供一种晶体管架构，其基极接触区域可以与集电极分离，因此允许显着降低晶体管的寄生效应。

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