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公开(公告)号：US08446777B2
公开(公告)日：2013-05-21
申请号：US13280618
申请日：2011-10-25
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/16 , G11C16/344
摘要： A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number
摘要翻译： 根据本发明的一个实施例的非易失性半导体存储器件包括存储单元阵列和控制单元。 控制单元被配置为控制擦除操作，擦除验证操作和升压操作的重复。 控制单元被配置为执行将存储单元从过擦除状态设置为第一阈值电压分布状态的软编程操作，当在一系列擦除操作中擦除电压应用的数量多于第一阈值电压分配状态时， 数字和小于第二个数字（第一个数字<第二个数字）。 当擦除电压应用的数量等于或小于第一数量或等于或大于第二数量时，控制单元被配置为不执行软编程操作。
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公开(公告)号：US20120281477A1
公开(公告)日：2012-11-08
申请号：US13308736
申请日：2011-12-01
申请人： Manabu Sakaniwa , Koki Ueno , Shigefumi Irieda , Eietsu Takahashi , Yasuhiro Shiino , Daisuke Kouno
发明人： Manabu Sakaniwa , Koki Ueno , Shigefumi Irieda , Eietsu Takahashi , Yasuhiro Shiino , Daisuke Kouno
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/3427
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of cell units each composed of a plurality of memory cells which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series and select transistors each connected to either end of the series connection, a voltage generator circuit which generates a voltage applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit.
摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，其包括多个单元单元，每个单元单元由多个存储单元构成，多个存储单元布置在多个位线和多个字线的交点处，并且其电流路径为 串联连接的晶体管和串联连接的任一端的晶体管，产生施加到存储单元阵列的电压的电压发生器电路以及控制存储单元阵列和电压发生器电路的控制电路。
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公开(公告)号：US20120269001A1
公开(公告)日：2012-10-25
申请号：US13280618
申请日：2011-10-25
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/16 , G11C16/344
摘要： A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number
摘要翻译： 根据本发明的一个实施例的非易失性半导体存储器件包括存储单元阵列和控制单元。 控制单元被配置为控制擦除操作，擦除验证操作和升压操作的重复。 控制单元被配置为执行将存储单元从过擦除状态设置为第一阈值电压分布状态的软编程操作，当在一系列擦除操作中擦除电压应用的数量多于第一阈值电压分配状态时， 数字和小于第二个数字（第一个数字<第二个数字）。 当擦除电压应用的数量等于或小于第一数量或等于或大于第二数量时，控制单元被配置为不执行软编程操作。
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公开(公告)号：US20120281487A1
公开(公告)日：2012-11-08
申请号：US13288485
申请日：2011-11-03
IPC分类号： G11C7/22
CPC分类号： G11C16/10 , G11C16/0483
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of memory cell units which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series, a voltage generator circuit which generates a voltage to be applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit. The control circuit, when writing data into the memory cell array, performs control so as to apply a first write pass voltage to unselected word lines in the memory cell units and, after a selected word line has reached a write voltage, further apply a voltage to the unselected word lines until a second write pass voltage higher than the first write pass voltage has been reached.
摘要翻译： 根据一个实施例，一种半导体存储器件包括：存储单元阵列，包括布置在多个位线和多个字线的交点处并且其电流通路串联连接的多个存储单元单元;电压发生器 产生施加到存储单元阵列的电压的电路，以及控制存储单元阵列和电压发生器电路的控制电路。 控制电路在将数据写入存储单元阵列时进行控制，以对存储单元单元中的未选字线施加第一写入通过电压，并且在所选字线达到写入电压之后，进一步施加电压 到未选择的字线，直到达到高于第一写入通过电压的第二写入通过电压。
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公开(公告)号：US08953371B2
公开(公告)日：2015-02-10
申请号：US13425121
申请日：2012-03-20
申请人： Yasuhiro Shiino , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/3418
摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
摘要翻译： 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。
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公开(公告)号：US08149631B2
公开(公告)日：2012-04-03
申请号：US12796964
申请日：2010-06-09
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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7.发明授权Nonvolatile semiconductor memory device using write pulses with different voltage gradients 有权非易失性半导体存储器件使用具有不同电压梯度的写入脉冲公开(公告)号：US08848447B2
公开(公告)日：2014-09-30
申请号：US13226826
申请日：2011-09-07
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3459
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：具有电可重写非易失性存储单元的存储单元阵列; 和控制单元。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入验证操作是用于验证数据写入是否完成的操作，并且升压操作是对 如果数据写入未完成，则提高写脉冲电压。 控制单元在写入操作期间，以第一梯度升高第一写入脉冲电压，然后以第二梯度提升第二写入脉冲电压，由此执行写入操作，第一写入脉冲电压至少包括写入脉冲 首先产生电压，第二写脉冲电压在第一写入脉冲电压之后产生，第二梯度大于第一梯度。
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公开(公告)号：US08531891B2
公开(公告)日：2013-09-10
申请号：US13346880
申请日：2012-01-10
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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公开(公告)号：US08385126B2
公开(公告)日：2013-02-26
申请号：US13246004
申请日：2011-09-27
申请人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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公开(公告)号：US08976597B2
公开(公告)日：2015-03-10
申请号：US13227050
申请日：2011-09-07
申请人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
CPC分类号： G11C16/16 , G11C16/3445 , G11C16/345
摘要： A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.
摘要翻译： 控制电路执行包括擦除脉冲施加操作和擦除验证操作的擦除操作。 擦除脉冲施加操作将擦除脉冲电压施加到存储单元，以将存储单元从写入状态改变为擦除状态。 擦除验证操作将擦除验证电压施加到存储器单元以判断存储器单元是否处于擦除状态。 当在一个擦除操作中执行擦除脉冲施加操作的次数达到第一数量时，控制电路改变擦除验证操作的执行条件。
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