公开(公告)号：US20090039930A1

公开(公告)日：2009-02-12

申请号：US12169972

申请日：2008-07-09

Applicant: Koji KUROKI ,  Yasuhiro TAKAI ,  Hiroki FUJISAWA

Inventor： Koji KUROKI ,  Yasuhiro TAKAI ,  Hiroki FUJISAWA

IPC: H03L7/06

CPC classification number: H03L7/087 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/10

Abstract: A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.

Abstract translation: DLL电路包括延迟线（CDL）（10），延迟线（10）以相对粗调的音调延迟时钟信号，延迟线（FDL）（20），以相当精细的调节间距延迟时钟信号;以及相位检测电路 以及控制延迟线（10,20）的延迟量的计数器控制电路。 计数器控制电路通过线性搜索方法控制延迟线（10），并通过二进制搜索方法来控制延迟线（20）。 结果，即使当用于调整延迟线（20）的计数信号的位数增加时，也可以高速地确定延迟量。

公开(公告)号：US20080197932A1

公开(公告)日：2008-08-21

申请号：US12031809

申请日：2008-02-15

Applicant: Yasuhiro TAKAI

Inventor： Yasuhiro TAKAI

IPC: H03K3/03

CPC classification number: H03K3/0322 ,  H03K5/133 ,  H03L7/0995

Abstract: A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals.

Abstract translation: 一种压控振荡器，其是差分环形振荡器型压控振荡器，其通过连接到级联差分延迟元件中，相位反相的差分时钟信号被输入到差分延迟元件中，并且通过偏置电压来控制流向差分延迟元件的电流 控制该差分时钟信号的延迟量，具有相位检测部分，该相位检测部分通过比较任何差分延迟元件的差分输出的输出电压和设置为检测异常运算的电压的参考电压来输出检测信号 以及设置在每个差分延迟元件处的交叉耦合电路，并且当输入检测信号时，放大该对差分输出端子之间的电位差。

公开(公告)号：US20080136485A1

公开(公告)日：2008-06-12

申请号：US12027766

申请日：2008-02-07

Applicant: Yasuhiro TAKAI ,  Shotaro KOBAYASHI

Inventor： Yasuhiro TAKAI ,  Shotaro KOBAYASHI

IPC: H03H11/26

CPC classification number: H03K5/133 ,  H03K5/135 ,  H03K2005/00058 ,  H03K2005/00241 ,  H03K2005/00247 ,  H03K2005/00273 ,  H03L7/0814 ,  H03L7/087

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract translation: 延迟电路包括具有多级延迟单元的第一延迟线电路，具有多级延迟单元的第二延迟线电路，与第一延迟单元的延迟单元的相应级相关联地设置的多个传输电路 延迟线电路，所述传送电路控制第一延迟线电路的延迟单元的输出到第二延迟线电路的延迟单元的相关级的传送。 第一延迟线电路各级的延迟单元反相输入信号。 第二延迟线电路的各级延迟单元包括接收与所讨论的延迟单元相关联的传送电路的输出信号的逻辑电路和将前一级的输出信号发送到后级的输出信号。 通过独立地选择输入信号的上升沿和下降沿的传播路径，使占空比变化。

公开(公告)号：US20070206430A1

公开(公告)日：2007-09-06

申请号：US11747552

申请日：2007-05-11

Applicant: Yasuhiro TAKAI

Inventor： Yasuhiro TAKAI

IPC: G11C29/08

CPC classification number: G11C29/50016 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40622 ,  G11C29/14

Abstract: Disclosed is a semiconductor memory device, in which the refresh period of a fail cell or cells is set so as to be shorter than that of the normal cells, comprises a control circuit for exercising control in such a manner that, if, when refreshing the cell of a first address, generated responsive to a refresh command, with an input control signal being of a first value, a second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the information ore-programmed in a refresh redundant ROM, the cell of the second address is refreshed, and also in such a manner that, if, with the input control signal of a second value, the second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the predetermined information, only the cell of the second address is refreshed, without refreshing the cell of the first address, generated responsive to the refresh command.

Abstract translation: 公开了一种半导体存储器件，其中将故障单元或单元的刷新周期设置为短于正常单元的刷新周期，包括用于以这样的方式进行控制的控制电路，即如果在刷新 被确定为响应于刷新命令产生的第一地址的单元，其中输入控制信号是第一值，对于来自第一地址的预定位不同的第二地址被确定为对应于故障单元 基于在刷新冗余ROM中编程的信息，第二地址的单元被刷新，并且还以这样的方式，如果利用第二值的输入控制信号，第二地址不同于 来自第一地址的预定比特的值被确定为对应于故障小区，基于预定信息，仅刷新第二地址的小区，而不刷新第一地址的小区，生成的响应 刷新命令。

公开(公告)号：US20130070536A1

公开(公告)日：2013-03-21

申请号：US13603020

申请日：2012-09-04

Applicant: Yasuhiro TAKAI

Inventor： Yasuhiro TAKAI

IPC: G11C7/10

CPC classification number: G11C11/4076 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal.

Abstract translation: 本文公开了一种包括定时控制电路的装置，其接收从外部提供的选通信号，以产生用作锁存数据信号的定时信号的内部选通信号。 定时控制电路的操作状态根据温度变化而改变，以便相对于选通信号的输入定时保持内部选通信号的输出定时。

公开(公告)号：US20080277863A1

公开(公告)日：2008-11-13

申请号：US12116493

申请日：2008-05-07

Applicant: Yasushi MATSUTOMO ,  Haruo SAYAMA ,  Kiwamu MORITA ,  Mikiya OKADA ,  Yasuhiro TAKAI

Inventor： Yasushi MATSUTOMO ,  Haruo SAYAMA ,  Kiwamu MORITA ,  Mikiya OKADA ,  Yasuhiro TAKAI

IPC: B65H3/06 ,  B65H7/12

CPC classification number: B65H3/0684 ,  B65H3/5261 ,  B65H2511/524 ,  B65H2515/34 ,  B65H2220/01 ,  B65H2220/02 ,  B65H2220/11

Abstract: A paper press member 240 configured to be capable of advancing and retracting with respect to a paper guide 220 is provided between a paper feed roller 234 and the front end in the paper feed direction of paper loaded in a manual feed tray 230. When a plurality of sheets of paper enter into the press-contact section between the paper feed roller 234 and a reverse roller 235, the reverse roller 235 is rotated in the reverse direction to retract the sheet on the reverse roller side to the manual feed tray 230. At this time, by causing the paper press member 240 to project from the upper surface of the paper guide 220, the sheet to be retracted and the paper press member 240 come into contact with each other, so that the travel amount of the sheet when retracting the sheet is reduced.

Abstract translation: 构造成能够相对于纸张引导件220前进和后退的纸按压构件240设置在供纸辊234和装载在手动进纸托盘230中的纸张的进纸方向上的前端之间。 当多张纸进入进纸辊234和反转辊235之间的压接部时，反转辊235沿相反方向转动，将反转辊侧的纸张收回到手动进纸盘 230。 此时，通过使纸按压部件240从纸引导件220的上表面突出，待缩回的片材和纸按压部件240彼此接触，使得片材的行进量 收缩纸张减少。

公开(公告)号：US20090066390A1

公开(公告)日：2009-03-12

申请号：US12205668

申请日：2008-09-05

Applicant: Akira IDE ,  Yasuhiro TAKAI ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Hiroaki NAKAYA

Inventor： Akira IDE ,  Yasuhiro TAKAI ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Hiroaki NAKAYA

IPC: H03H11/26

CPC classification number: H03K5/15033

Abstract: Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.

Abstract translation: 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m.T1 + n。（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m.T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n的精细定时信号（T2 / L）。 m和n的值可以由寄存器设置。

公开(公告)号：US20090016127A1

公开(公告)日：2009-01-15

申请号：US12170730

申请日：2008-07-10

Applicant: Koji KUROKI ,  Yasuhiro TAKAI

Inventor： Koji KUROKI ,  Yasuhiro TAKAI

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/087

Abstract: A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.

Abstract translation: 占空比检测电路包括放电晶体管，充电晶体管，检测线和检测这些检测线的电位差的比较器电路，还包括根据内部时钟信号控制放电晶体管和充电晶体管的门电路 的偶数周期。 结果，响应于偶数周期的内部时钟信号，检测线被充电和放电。 因此，占空比检测电路可以应用于多相DLL电路，并且可以充分确保出现在检测线中的电位差。

公开(公告)号：US20080258380A1

公开(公告)日：2008-10-23

申请号：US11863414

申请日：2007-09-28

Applicant: Yoshinobu OKUMURA ,  Yasushi MATSUTOMO ,  Haruo SAYAMA ,  Yasunobu OHKAWA ,  Michihiro YAMASHITA ,  Yuriko KAMEI ,  Yasuhiro TAKAI

Inventor： Yoshinobu OKUMURA ,  Yasushi MATSUTOMO ,  Haruo SAYAMA ,  Yasunobu OHKAWA ,  Michihiro YAMASHITA ,  Yuriko KAMEI ,  Yasuhiro TAKAI

IPC: B65H7/02

CPC classification number: B65H5/062 ,  B65H7/20 ,  B65H2220/09 ,  B65H2404/14 ,  B65H2511/20 ,  B65H2511/514 ,  B65H2513/10 ,  B65H2513/50 ,  B65H2557/23 ,  B65H2801/06 ,  B65H2220/03 ,  B65H2220/01 ,  B65H2220/02

Abstract: A sheet feeder has a feed passage and includes feed roller pairs, sensors, and a controller. The feed roller pairs are arranged along the feed passage and feed sheets of paper in a feed direction along the passage by nipping the sheets. Each of the sensors is fitted at or near one of the feed roller pairs and senses a specified point on each of the sheets when the sheet is nipped by at least the associated roller pair. The controller includes a memory for storing reference feed timings as proper feed timings at each of which the specified points on the sheets should pass one of the sensors. The controller finds the real feed timing when each of the sensors senses the specified point on the sheet nipped by at least the associated roller pair. When each of the sensors senses the specified point on the sheet nipped by at least the associated roller pair, the controller finds the time difference between the associated reference feed timing and the associated real feed timing and controls, according to the found time difference, the feed speed at which the feed roller pair or pairs nipping the sheet feed it.

Abstract translation: 送纸器具有进给通道，并且包括进给辊对，传感器和控制器。 馈送辊对沿着进给通道布置，并且通过夹住纸张沿着通道沿进给方向馈送纸张。 每个传感器安装在进给辊对中或附近，并且当片材被至少相关联的辊对夹持时，感测每个片材上的指定点。 控制器包括用于将参考馈送定时存储为适当的馈送定时的存储器，其中片材上的指定点将通过其中一个传感器。 当每个传感器感测到由​​至少相关联的辊对夹持的片材上的指定点时，控制器找到实际的进给定时。 当每个传感器感测至少被相关联的辊对夹紧的片材上的指定点时，控制器根据所发现的时间差找到相关联的基准馈送定时和相关联的实际馈送定时之间的时间差并进行控制， 进给辊对或夹紧片材的进给速度进给。

公开(公告)号：US20070210843A1

公开(公告)日：2007-09-13

申请号：US11682662

申请日：2007-03-06

Applicant: Yasuhiro TAKAI

Inventor： Yasuhiro TAKAI

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/107

Abstract: A DLL circuit comprising: delay circuits which output first and second delayed clock signals obtained by delaying the reference clock signal by a delay times selected according to control signals; an interpolation circuit which interpolates a phase difference between the delayed clock signals to output an internal clock signal; an output circuit which generates a predetermined signal; a dummy output circuit which has the same transmission characteristics as the output circuit and outputs a feedback clock signal having the same phase as the predetermined signal; a phase comparison circuit which compares phases of the reference clock signal and the feedback clock signal; delay control circuits which controls the control signals in a direction where both phases are equal; wherein the delay time of the second delayed clock signal is larger than the first delayed clock signal by an amount equivalent to one cycle of the reference clock signal.

Abstract translation: 一种DLL电路，包括：延迟电路，其输出通过将所述参考时钟信号延迟由根据控制信号选择的延迟时间而获得的第一和第二延迟时钟信号; 内插电路，其对所述延迟的时钟信号之间的相位差进行内插以输出内部时钟信号; 产生预定信号的输出电路; 虚拟输出电路，其具有与所述输出电路相同的传输特性，并输出具有与所述预定信号相同相位的反馈时钟信号; 比较参考时钟信号和反馈时钟信号的相位的相位比较电路; 延迟控制电路，其在两相相等的方向上控制控制信号; 其中所述第二延迟时钟信号的延迟时间大于所述第一延迟时钟信号相当于所述参考时钟信号的一个周期的量。