公开(公告)号：US09299700B2

公开(公告)日：2016-03-29

申请号：US14639494

申请日：2015-03-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

摘要翻译： 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US20160163718A1

公开(公告)日：2016-06-09

申请号：US15047181

申请日：2016-02-18

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L27/11 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20150325575A1

公开(公告)日：2015-11-12

申请号：US14639494

申请日：2015-03-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

摘要翻译： 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US09548309B2

公开(公告)日：2017-01-17

申请号：US15047181

申请日：2016-02-18

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

摘要翻译： 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US09755079B2

公开(公告)日：2017-09-05

申请号：US15000495

申请日：2016-01-19

申请人： Sang-Jine Park ,  Keun-Hee Bai ,  Kyoung-Hwan Yeo ,  Bo-Un Yoon ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Ha-Young Jeon ,  Seung-Seok Ha

发明人： Sang-Jine Park ,  Keun-Hee Bai ,  Kyoung-Hwan Yeo ,  Bo-Un Yoon ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Ha-Young Jeon ,  Seung-Seok Ha

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/7848

摘要： Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

公开(公告)号：US20160284699A1

公开(公告)日：2016-09-29

申请号：US15007882

申请日：2016-01-27

申请人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

发明人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L27/0886 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/6656

摘要： A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

摘要翻译： 提供半导体器件。 半导体器件包括限定衬底上的沟槽并包括上部和下部的栅极间隔物，栅极绝缘膜，其沿着沟槽的侧壁和底表面延伸并且不与所述沟槽的上部接触 栅极间隔物，沿着沟槽的侧壁和底面在栅极绝缘膜上延伸的下部导电膜，并且不与栅极间隔物的上部重叠，并且栅极绝缘的最上部的上部导电膜 在下导电膜上的膜。

公开(公告)号：US08709942B2

公开(公告)日：2014-04-29

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US20130023119A1

公开(公告)日：2013-01-24

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US20130115759A1

公开(公告)日：2013-05-09

申请号：US13561245

申请日：2012-07-30

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/20

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/78 ,  H01L29/7848

摘要： Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

摘要翻译： 提供制造半导体器件的方法，其包括提供包括具有栅极图案的第一区域和具有填充第一沟槽的第一沟槽和绝缘层的第二区域的衬底。 通过蚀刻绝缘层的一部分露出第一沟槽的侧壁的一部分，并且在栅极图案的侧壁上形成第一间隔物。 第二间隔件形成在第一沟槽的暴露的侧壁上，其中第一间隔件和第二间隔件同时形成。

公开(公告)号：US09754880B2

公开(公告)日：2017-09-05

申请号：US15016376

申请日：2016-02-05

申请人： Jae-Jik Baek ,  Kee-Sang Kwon ,  Sang-Jine Park ,  Bo-Un Yoon

发明人： Jae-Jik Baek ,  Kee-Sang Kwon ,  Sang-Jine Park ,  Bo-Un Yoon

IPC分类号： H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L23/528 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/088 ,  H01L27/0886

摘要： The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.