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    CHEMICAL SUPPLIER, PROCESSING APPARATUS INCLUDING THE CHEMICAL SUPPLIER
    1.
    发明申请
    CHEMICAL SUPPLIER, PROCESSING APPARATUS INCLUDING THE CHEMICAL SUPPLIER 审中-公开
    化学供应商，包括化学供应商的加工设备

    公开(公告)号：US20140231010A1

    公开(公告)日：2014-08-21

    申请号：US14183994

    申请日：2014-02-19

    申请人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

    发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

    IPC分类号： H01L21/67

    CPC分类号： H01L21/67075 ,  H01L21/67017 ,  H01L21/6708

    摘要： A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.

    摘要翻译： 化学品供应商包括在室温下含有化学混合物的化学容器，化学容器的内部空间与周围环境分离，供应管线，化学混合物通过该供应管线从化学容器供应到处理室，一体式加热器 定位在供应管线上并将供应管线中的化学混合物加热至处理温度，以及驱动化学混合物以将化学混合物移向处理室的电源。

    Semiconductor devices and methods of manufacturing the same
    2.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08803248B2

    公开(公告)日：2014-08-12

    申请号：US13241324

    申请日：2011-09-23

    申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

    发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

    IPC分类号： H01L27/088

    CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

    摘要： Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

    摘要翻译： 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

    Methods for fabricating semiconductor devices
    3.
    发明授权
    Methods for fabricating semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08709942B2

    公开(公告)日：2014-04-29

    申请号：US13488478

    申请日：2012-06-05

    申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

    发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

    摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

    摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
    4.
    发明申请
    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20130023119A1

    公开(公告)日：2013-01-24

    申请号：US13488478

    申请日：2012-06-05

    申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

    发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

    摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

    摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

    Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers
    5.
    发明授权
    Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers 有权
    使用稀释的氢氟酸来形成场效应晶体管以去除牺牲性氮化物间隔物的方法

    公开(公告)号：US07902082B2

    公开(公告)日：2011-03-08

    申请号：US11858535

    申请日：2007-09-20

    申请人： Sang Jine Park ,  Richard O. Henry ,  Yong Siang Tan ,  O Sung Kwon ,  Oh Jung Kwon

    发明人： Sang Jine Park ,  Richard O. Henry ,  Yong Siang Tan ,  O Sung Kwon ,  Oh Jung Kwon

    IPC分类号： H01L21/302

    CPC分类号： H01L29/66636 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7843

    摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成具有栅电极的场效应晶体管，在栅电极的相对侧壁上的牺牲氮化物间隔物和与牺牲氮化物间隔物自对准的源/漏区。 使用具有氮化物至氧化物蚀刻选择性的稀释氢氟酸溶液选择性地除去牺牲氮化物间隔物。 为了增加场效应晶体管的沟道内的电荷载流子迁移率，在栅电极的相对侧壁上形成应力感应电绝缘层。 该绝缘层被配置为在通道中引起净拉伸应力（NMOS）或压缩应力（PMOS）。

    Method of fabricating semiconductor device
    10.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09054210B2

    公开(公告)日：2015-06-09

    申请号：US13479679

    申请日：2012-05-24

    申请人： Sang-Jine Park ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Won-Sang Choi

    发明人： Sang-Jine Park ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Won-Sang Choi

    IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311

    CPC分类号： H01L21/823425 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.

    摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底上形成包括栅极和源极和漏极区的晶体管，在所述晶体管上形成层间绝缘膜，在所述层间绝缘膜中形成接触孔以暴露出 源极和漏极区域的顶表面，并且在接触孔和源极和漏极区域的暴露顶表面之间的界面处形成薄膜。 该方法还包括通过在非等离子体气氛中进行蚀刻工艺来选择性地去除薄膜的至少一部分，在选择性地去除薄膜的至少一部分的源区和漏区上形成欧姆接触膜， 以及通过用导电材料填充接触孔来形成接触塞。