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    METHOD OF FORMING FINE PATTERN AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE METHOD
    2.
    发明申请
    METHOD OF FORMING FINE PATTERN AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE METHOD 有权
    形成微细图案的方法和使用该方法制造集成电路装置的方法

    公开(公告)号：US20160172187A1

    公开(公告)日：2016-06-16

    申请号：US14958072

    申请日：2015-12-03

    Applicant: Jeong-ju PARK ,  Seung-chul KWON ,  Eun-sung KIM ,  Jae-woo NAM ,  Shi-yong YI ,  Hyun-woo KIM

    Inventor： Jeong-ju PARK ,  Seung-chul KWON ,  Eun-sung KIM ,  Jae-woo NAM ,  Shi-yong YI ,  Hyun-woo KIM

    IPC: H01L21/027 ,  H01L21/311

    CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  C08L53/00 ,  G03F7/002 ,  G03F7/0035 ,  G03F7/165 ,  G03F7/2022 ,  G03F7/2059 ,  G03F7/40 ,  H01L21/02112 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/10855

    Abstract: A method of forming a fine pattern includes forming pillar-shaped guides regularly arranged on a feature layer, forming a block copolymer layer on the feature layer around the pillar-shaped guides, phase separating the block copolymer layer, forming first domains regularly arranged on the feature layer with the pillar-shaped guides, forming a second domain on the feature layer surrounding the pillar-shaped guides and the first domains, removing the first domains, and forming holes corresponding with the first domains in the feature layer by etching the feature layer using the pillar-shaped guides and the second domain as etch masks. The block copolymer layer includes a polymer blend having first and second polymer blocks having first and second repeat units, respectively, a first homopolymer and a second homopolymer. The first domains include the first polymer block and the first homopolymer, and the second domain includes the second polymer block and the second homopolymer.

    Abstract translation: 形成精细图案的方法包括：形成规则排列在特征层上的柱状引导件，在柱状引导件周围的特征层上形成嵌段共聚物层，相分离嵌段共聚物层，形成规则排列在第 具有柱状引导件的特征层，在围绕柱状引导件和第一域的特征层上形成第二结构域，通过蚀刻特征层来去除第一区域并形成与特征层中的第一区域相对应的孔 使用柱形引导件和第二域作为蚀刻掩模。 嵌段共聚物层包括聚合物共混物，其具有分别具有第一和第二重复单元的第一和第二聚合物嵌段，第一均聚物和第二均聚物。 第一结构域包括第一聚合物嵌段和第一均聚物，第二结构域包括第二聚合物嵌段和第二均聚物。

    Method of forming fine patterns of semiconductor device by using double patterning process which uses acid diffusion
    3.
    发明授权
    Method of forming fine patterns of semiconductor device by using double patterning process which uses acid diffusion 有权
    通过使用酸扩散的双重图案化工艺形成半导体器件精细图案的方法

    公开(公告)号：US08431331B2

    公开(公告)日：2013-04-30

    申请号：US12267687

    申请日：2008-11-10

    Applicant: Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

    Inventor： Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

    IPC: G03F7/40

    CPC classification number: H01L21/027 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/32139

    Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.

    Abstract translation: 提供了根据使用酸扩散的双重图案化工艺形成半导体器件的精细图案的方法。 在该方法中，在基板上形成多个第一掩模图案以彼此分离。 在多个第一掩模图案的每一个的侧壁和上表面上形成包括酸源的封盖膜。 在封盖膜上形成第二掩模层。 通过将从酸源获得的酸从封盖膜扩散到第二掩模层中，在第二掩模层内形成多个酸扩散区。 多个第二掩模图案由除去第二掩模层的酸扩散区域之后残留在第一间隙中的第二掩模层的残留部分形成。

    Method of fine patterning semiconductor device
    5.
    发明授权
    Method of fine patterning semiconductor device 有权
    精细图案化半导体器件的方法

    公开(公告)号：US08029688B2

    公开(公告)日：2011-10-04

    申请号：US12217784

    申请日：2008-07-09

    Applicant: Shi-Yong Yi ,  Myeong-Cheol Kim ,  Dong-Ki Yoon ,  Kyung-Yub Jeon ,  Ji-Hoon Cha

    Inventor： Shi-Yong Yi ,  Myeong-Cheol Kim ,  Dong-Ki Yoon ,  Kyung-Yub Jeon ,  Ji-Hoon Cha

    IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/312 ,  H01L21/32139

    Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.

    Abstract translation: 为了在集成电路制造期间进行图案化，形成第一掩模结构的第一图案，并且在第一掩模结构的暴露表面上形成缓冲层。 此外，在第一掩蔽结构的侧壁处的缓冲层之间的凹部中形成第二掩模结构的第二图案。 此外，第一掩模结构和掩模结构由各自含高含碳材料的旋涂形成。 这样的第一和第二掩模结构以比传统光刻法更高的间距对目标层进行图案化。

    Method of forming patterns of semiconductor device
    7.
    发明申请
    Method of forming patterns of semiconductor device 有权
    形成半导体器件图案的方法

    公开(公告)号：US20100248492A1

    公开(公告)日：2010-09-30

    申请号：US12655344

    申请日：2009-12-29

    Applicant: Dong-ki Yoon ,  Shi-yong Yi ,  Seong-woon Choi ,  Seok-hwan Oh ,  Kwang-sub Yoon ,  Myeong-cheol Kim ,  Young-ju Park

    Inventor： Dong-ki Yoon ,  Shi-yong Yi ,  Seong-woon Choi ,  Seok-hwan Oh ,  Kwang-sub Yoon ,  Myeong-cheol Kim ,  Young-ju Park

    IPC: H01L21/302

    CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/115 ,  H01L27/11517

    Abstract: A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask.

    Abstract translation: 通过使用含碳（C）的膜来形成半导体器件的精细图案的方法包括在包括第一和第二区域的衬底上形成蚀刻靶膜; 在所述第一区域中的所述蚀刻目标膜上形成多个第一含C膜的图案; 形成覆盖所述多个第一含C膜图案的顶表面和侧表面的缓冲层; 形成第二含C膜; 去除第二区域中的第二含C膜; 通过去除第一和第二区域中的缓冲层的一部分来暴露多个第一含C膜的图案; 并且通过使用多个第一含C膜膜图案和残留在第一区域中的第二含C膜的部分来蚀刻蚀刻目标膜作为蚀刻掩模。

    Method of forming fine patterns using a block copolymer
    8.
    发明申请
    Method of forming fine patterns using a block copolymer 有权
    使用嵌段共聚物形成精细图案的方法

    公开(公告)号：US20090042146A1

    公开(公告)日：2009-02-12

    申请号：US12076491

    申请日：2008-03-19

    Applicant: Kyoung Taek Kim ,  Hyun Woo Kim ,  Sang Ouk Kim ,  Shi Yong Yi ,  Seong Woon Choi

    Inventor： Kyoung Taek Kim ,  Hyun Woo Kim ,  Sang Ouk Kim ,  Shi Yong Yi ,  Seong Woon Choi

    IPC: G03F7/20

    CPC classification number: B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00

    Abstract: A method of patterning a substrate includes processing first regions of the substrate to form a first pattern, the first regions defining a second region between adjacent first regions, arranging a block copolymer on the first and second regions, the block copolymer including a first component and a second component, the first component of the block copolymer being aligned on the first regions, and selectively removing one of the first component and the second component of the block copolymer to form a second pattern having a pitch that is less than a pitch of a first region and an adjacent second region.

    Abstract translation: 图案化衬底的方法包括处理衬底的第一区域以形成第一图案，第一区域限定相邻第一区域之间的第二区域，在第一和第二区域上布置嵌段共聚物，所述嵌段共聚物包括第一组分和 第二组分，嵌段共聚物的第一组分在第一区域上对准，并且选择性地除去嵌段共聚物的第一组分和第二组分中的一种，以形成具有小于间距的沥青的第二图案 第一区域和相邻的第二区域。

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