公开(公告)号：US20090212863A1

公开(公告)日：2009-08-27

申请号：US12370629

申请日：2009-02-13

申请人： Yoshiteru ISHIMARU

发明人： Yoshiteru ISHIMARU

IPC分类号： H03F3/45

CPC分类号： H03F3/191 ,  H03F1/302 ,  H03F1/56 ,  H03F2200/18 ,  H03F2200/451

摘要： In the power amplifier of the invention, at a start of power amplification by an amplifier transistor 103 serving as an amplification section, a speedup circuit 122 transiently increases a bias which is fed to the amplifier transistor 103 via a bias power source section composed of a bias circuit 111 and a power source circuit 112. As a result, the power amplification factor of the amplifier transistor 103 is transiently increased at the start of power amplification by the amplifier transistor 103. Thus, the time elapsing until temperature variations due to heat generation of the amplifier transistor 103 come to an equilibrium on the whole circuit is shortened, with a result of reduced distortion of the amplification signal such as a modulated-wave signal. Accordingly, in the invention, it becomes possible to suppress distortion increases of an amplification signal due to heat generation at the start time without using any temperature sensing element.

摘要翻译： 在本发明的功率放大器中，在用作放大部分的放大器晶体管103进行功率放大的开始时，加速电路122暂时增加通过偏置电源部分馈送到放大器晶体管103的偏压 偏置电路111和电源电路112.结果，放大晶体管103的功率放大开始时放大晶体管103的功率放大系数瞬间增加。因此，直到由于发热引起的温度变化之前的时间 放大晶体管103在整个电路上达到平衡被缩短，结果是诸如调制波信号的放大信号的失真减小。 因此，在本发明中，可以抑制由于在开始时的发热而引起的放大信号的变形增大，而不使用任何温度检测元件。

公开(公告)号：US07573336B2

公开(公告)日：2009-08-11

申请号：US12010592

申请日：2008-01-28

申请人： Yoshiteru Ishimaru ,  Motoko Furukawa

发明人： Yoshiteru Ishimaru ,  Motoko Furukawa

IPC分类号： H03F3/04

CPC分类号： H03F1/302 ,  H03F3/211 ,  H03F2200/18 ,  H03F2200/318 ,  H03F2200/411 ,  H03F2200/447 ,  H03G1/04

摘要： A bias circuit 22 in a power amplifier 1 is provided with a VBE-controlled voltage source circuit 20 and a Nagata current mirror circuit 21. The Nagata current mirror circuit 21 includes a transistor Tr5 and a transistor Tr6. The transistor Tr5 has its emitter grounded, its base connected to a control input terminal 17 via a resistor R3, and its collector connected to that base via a resistor R4. The transistor Tr6 has its emitter grounded, its base connected to the collector of the transistor Tr5, and its collector connected to the base of the transistor Tr3. The arrangement is capable of compensating both the temperature characteristics of the gain of the power amplifier 1 and the control input voltage characteristics of the gain of the power amplifier 1. In other words, the arrangement is capable of reducing the temperature dependence and control input voltage dependence of the gain of the power amplifier 1.

摘要翻译： 功率放大器1中的偏置电路22设置有VBE控制的电压源电路20和Nagata电流镜电路21. Nagata电流镜电路21包括晶体管Tr5和晶体管Tr6。 晶体管Tr5的发射极接地，其基极经由电阻器R3连接到控制输入端子17，其集电极通过电阻器R4连接到该基极。 晶体管Tr6的发射极接地，其基极连接到晶体管Tr5的集电极，其集电极连接到晶体管Tr3的基极。 该装置能够补偿功率放大器1的增益的温度特性和功率放大器1的增益的控制输入电压特性。换句话说，该装置能够降低温度依赖性并且控制输入电压 功率放大器增益的依赖性1。

公开(公告)号：US06593604B2

公开(公告)日：2003-07-15

申请号：US09772941

申请日：2001-01-31

申请人： Yoshiteru Ishimaru

发明人： Yoshiteru Ishimaru

IPC分类号： H01L310328

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

摘要： An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damage during formation of the protrusion by etching or during later fabricating processes. Penetration of moisture through damaged places is eliminated. A base ohmic electrode is continuously formed on the first and second emitter layers on the external base region up to the protrusion. Thus, the protrusion is reinforced so as to be further hard to damage. By ensuring a large area for the base ohmic electrode, an alignment margin can be taken during formation of a base lead electrode.

摘要翻译： 异质结双极晶体管的发射极具有由第一发射极层和第二发射极层形成并突出到外部基极区域外部的双层突起。 总厚度为50nm的突起足以防止在通过蚀刻形成突起或在后续制造工艺期间的损坏。 消除了通过受损位置渗透水分。 基极欧姆电极连续地形成在外部基极区域上的第一和第二发射极层直到突出部分。 因此，突起被加强以进一步难以损坏。 通过确保基极欧姆电极的大面积，可以在形成基极引线电极期间采取取向余量。

公开(公告)号：US06239608B1

公开(公告)日：2001-05-29

申请号：US09330457

申请日：1999-06-11

申请人： Yu Zhu ,  Yoshiteru Ishimaru ,  Masafumi Shimizu

发明人： Yu Zhu ,  Yoshiteru Ishimaru ,  Masafumi Shimizu

IPC分类号： G01R3126

CPC分类号： H01L22/14 ,  G01R31/2632

摘要： A method for analyzing a Schottky junction of the present invention includes the step of obtaining electrical field dependence of the Schottky barrier height which shows a degree of dependence of the Schottky barrier height of the Schottky junction formed on a semiconductor wafer on an electrical field applied to an interface of the Schottky junction in a case where a reverse bias is applied to the Schottky junction. The method includes the steps of: applying the reverse bias of a plurality of voltage values to the Schottky junction; measuring a plurality of current values of a current flowing through the Schottky junction and a plurality of capacitance values of the Schottky junction, corresponding to the reverse bias of the plurality of voltage values; obtaining current-voltage characteristics and capacitance-voltage characteristics of the Schottky junction based on the plurality of current values and the plurality of capacitance values; calculating depletion layer charge-voltage characteristics showing a correlation between an accumulated charge in a depletion layer and a voltage by integrating the capacitance-voltage characteristics with respect to a voltage; and obtaining the electrical field dependence of the Schottky barrier height based on the current-voltage characteristics and the depletion layer charge-voltage characteristics.

摘要翻译： 用于分析本发明的肖特基结的方法包括获得肖特基势垒高度的电场依赖性的步骤，其显示形成在半导体晶片上的肖特基结的肖特基势垒高度与施加到 在将反向偏压施加到肖特基结的情况下的肖特基结的界面。 该方法包括以下步骤：将多个电压值的反向偏压施加到肖特基结; 测量流过所述肖特基结的电流的多个电流值和对应于所述多个电压值的反向偏置的所述肖特基结的多个电容值; 基于所述多个电流值和所述多个电容值，获得所述肖特基结的电流 - 电压特性和电容 - 电压特性; 计算通过将电容 - 电压特性相对于电压进行积分而示出耗尽层中的累积电荷与电压之间的相关性的耗尽层电荷 - 电压特性; 并且基于电流 - 电压特性和耗尽层电荷 - 电压特性获得肖特基势垒高度的电场依赖性。

公开(公告)号：US5912480A

公开(公告)日：1999-06-15

申请号：US665510

申请日：1996-06-18

申请人： Yu Zhu ,  Yoshiteru Ishimaru ,  Naoki Takahashi ,  Masafumi Shimizu

发明人： Yu Zhu ,  Yoshiteru Ishimaru ,  Naoki Takahashi ,  Masafumi Shimizu

IPC分类号： H01L29/872 ,  H01L21/338 ,  H01L29/205 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328

CPC分类号： H01L29/205 ,  H01L29/475 ,  H01L29/7783

摘要： A heterojunction semiconductor device includes a first Schottky contact layer made of a first semiconductor, a second Schottky contact layer made of a second semiconductor and a metal electrode. The first Schottky contact layer, the second Schottky contact layer and the metal electrode are laminated in this order on a semiconductor substrate or on a main structure of a semiconductor device laminated on a semiconductor substrate from the substrate side or from the main structure side. The first Schottky contact layer serves as a barrier layer toward the second Schottky contact layer, and a layer thickness of the second Schottky contact layer is greater than the mean free pass of carriers in the second Schottky contact layer.

摘要翻译： 异质结半导体器件包括由第一半导体制成的第一肖特基接触层，由第二半导体制成的第二肖特基接触层和金属电极。 第一肖特基接触层，第二肖特基接触层和金属电极依次层叠在半导体基板上或层叠在半导体基板上的从基板侧或主结构侧的半导体器件的主结构上。 第一肖特基接触层用作朝向第二肖特基接触层的阻挡层，并且第二肖特基接触层的层厚度大于第二肖特基接触层中载流子的平均自由程。

公开(公告)号：US5876901A

公开(公告)日：1999-03-02

申请号：US592966

申请日：1996-01-29

申请人： Yoshiteru Ishimaru

发明人： Yoshiteru Ishimaru

IPC分类号： G03F7/012 ,  G03F7/039 ,  H01L21/027 ,  H01L21/285 ,  H01L21/338 ,  H01L29/41 ,  H01L29/812 ,  G03F7/00

CPC分类号： H01L21/0277 ,  H01L21/0275 ,  H01L21/28512 ,  H01L21/28581 ,  H01L21/28587 ,  Y10S430/143

摘要： The method for fabricating a semiconductor device according to the present includes the steps of:forming an opening in an electron beam resist layer formed on a semiconductor substrate;forming an opening in a photoresist layer formed on the electron beam resist layer in such a manner that the opening formed at the electron beam layer is exposed, and that the opening formed in the photoresist layer has a larger dimension than that of the opening formed in the electron beam resist layer; andforming an electrode having a T-shaped cross section by depositing an electrode material via the two openings,wherein the electron beam resist layer is formed of a polymethacrylate type electron beam resist, and the photoresist layer is formed of a styrene resin type negative resist containing a phenolic hydroxyl group.

摘要翻译： 根据本发明的半导体器件的制造方法包括以下步骤：在形成在半导体衬底上的电子束抗蚀剂层中形成开口; 在形成在电子束抗蚀剂层上的光致抗蚀剂层中形成开口，使得形成在电子束层处的开口露出，形成在光刻胶层中的开口的尺寸大于形成在 电子束抗蚀剂层; 以及通过两个开口沉积电极材料形成具有T形横截面的电极，其中电子束抗蚀层由聚甲基丙烯酸酯型电子束抗蚀剂形成，光致抗蚀剂层由苯乙烯树脂型负性抗蚀剂 含有酚羟基。

公开(公告)号：US20080186099A1

公开(公告)日：2008-08-07

申请号：US12010592

申请日：2008-01-28

申请人： Yoshiteru Ishimaru ,  Motoko Furukawa

发明人： Yoshiteru Ishimaru ,  Motoko Furukawa

IPC分类号： H03G3/10 ,  H03F3/68

CPC分类号： H03F1/302 ,  H03F3/211 ,  H03F2200/18 ,  H03F2200/318 ,  H03F2200/411 ,  H03F2200/447 ,  H03G1/04

摘要： A bias circuit 22 in a power amplifier 1 is provided with a VBE-controlled voltage source circuit 20 and a Nagata current mirror circuit 21. The Nagata current mirror circuit 21 includes a transistor Tr5 and a transistor Tr6. The transistor Tr5 has its emitter grounded, its base connected to a control input terminal 17 via a resistor R3, and its collector connected to that base via a resistor R4. The transistor Tr6 has its emitter grounded, its base connected to the collector of the transistor Tr5, and its collector connected to the base of the transistor Tr3. The arrangement is capable of compensating both the temperature characteristics of the gain of the power amplifier 1 and the control input voltage characteristics of the gain of the power amplifier 1. In other words, the arrangement is capable of reducing the temperature dependence and control input voltage dependence of the gain of the power amplifier 1.

摘要翻译： 功率放大器1中的偏置电路22设置有VBE控制电压源电路20和Nagata电流镜电路21. Nagata电流镜电路21包括晶体管Tr 5和晶体管Tr 6.晶体管Tr 5具有 其发射极接地，其基极通过电阻器R 3连接到控制输入端子17，其集电极经由电阻器R 4连接到该基极。晶体管Tr 6的发射极接地，其基极连接到晶体管的集电极 Tr 5，其集电极连接到晶体管Tr 3的基极。该装置能够补偿功率放大器1的增益的温度特性和功率放大器1的增益的控制输入电压特性。 换句话说，该装置能够降低功率放大器1的增益的温度依赖性和控制输入电压依赖性。

公开(公告)号：US20070024370A1

公开(公告)日：2007-02-01

申请号：US11493758

申请日：2006-07-27

申请人： Michitoshi Hirata ,  Yoshiteru Ishimaru

发明人： Michitoshi Hirata ,  Yoshiteru Ishimaru

IPC分类号： H03G3/10

CPC分类号： H03F3/189 ,  H03F1/30 ,  H03F1/32

摘要： A variable impedance circuit includes a capacitor and a MOSFET and is connected between the base of a bipolar transistor and a ground node. The capacitor acts to the open for a direct-current component. The MOSFET varies impedance for an alternate-current component. A base voltage ration portion includes first and second resistors, which set a bias applied to the base of the bipolar transistor. More specifically, the base voltage generation portion divides an operating voltage supplied through a voltage terminal by a ratio of the first and second resistors to generate a base voltage of the bipolar transistor.

摘要翻译： 可变阻抗电路包括电容器和MOSFET，并连接在双极晶体管的基极和接地节点之间。 电容器对直流分量起作用。 MOSFET会改变交流分量的阻抗。 基极电压比例部分包括第一和第二电阻，其设置施加到双极晶体管的基极的偏置。 更具体地，基极电压产生部分通过电压端子提供的工作电压除以第一和第二电阻器的比率，以产生双极晶体管的基极电压。

公开(公告)号：US06611008B2

公开(公告)日：2003-08-26

申请号：US09522825

申请日：2000-03-10

申请人： John Kevin Twynam ,  Yoshiteru Ishimaru

发明人： John Kevin Twynam ,  Yoshiteru Ishimaru

IPC分类号： H01L310328

CPC分类号： H01L29/7371 ,  H01L29/0817 ,  H01L29/7304

摘要： A heterojunction bipolar transistor has a stack comprised of a base layer, an emitter layer and a ballast layer made of AlGaAs. The emitter layer is comprised of a single layer or a multiplicity of layers, and at least one of which is comprised of a material that prevents hole injection from the base layer into the ballast layer. Thus, the hole injection from the base layer into the emitter layer is prevented. Accordingly, it is able to prevent the conductivity modulation of the ballast layer that is the cause of a deterioration in temperature characteristics.

公开(公告)号：US5942909A

公开(公告)日：1999-08-24

申请号：US893044

申请日：1997-07-15

申请人： Yu Zhu ,  Yoshiteru Ishimaru ,  Masafumi Shimizu

发明人： Yu Zhu ,  Yoshiteru Ishimaru ,  Masafumi Shimizu

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L22/14 ,  G01R31/2632

摘要： A method for analyzing a Schottky junction includes the step of obtaining electrical field dependence of the Schottky barrier height which shows a degree of dependence of the Schottky barrier height of the Schottky junction formed on a semiconductor wafer on an electrical field applied to an interface of the Schottky junction in a case where a reverse bias is applied to the Schottky junction. The method includes the steps of: applying the reverse bias of a plurality of voltage values to the Schottky junction; measuring a plurality of current values of a current flowing through the Schottky junction and a plurality of capacitance values of the Schottky junction, corresponding to the reverse bias of the plurality of voltage values; obtaining current-voltage characteristics and capacitance-voltage characteristics of the Schottky junction based on the plurality of current values and the plurality of capacitance values; calculating depletion layer charge-voltage characteristics showing a correlation between an accumulated charge in a depletion layer and a voltage by integrating the capacitance-voltage characteristics with respect to a voltage; and obtaining the electrical field dependence of the Schottky barrier height based on the current-voltage characteristics and the depletion layer charge-voltage characteristics.

摘要翻译： 用于分析肖特基结的方法包括获得肖特基势垒高度的电场依赖性的步骤，其显示了形成在半导体晶片上的肖特基结的肖特基势垒高度与施加到半导体晶片的界面的电场的依赖程度 在肖特基结上施加反向偏压的情况下的肖特基结。 该方法包括以下步骤：将多个电压值的反向偏压施加到肖特基结; 测量流过所述肖特基结的电流的多个电流值和对应于所述多个电压值的反向偏置的所述肖特基结的多个电容值; 基于所述多个电流值和所述多个电容值，获得所述肖特基结的电流 - 电压特性和电容 - 电压特性; 计算通过将电容 - 电压特性相对于电压进行积分而示出耗尽层中的累积电荷与电压之间的相关性的耗尽层电荷 - 电压特性; 并且基于电流 - 电压特性和耗尽层电荷 - 电压特性获得肖特基势垒高度的电场依赖性。