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    Silicon on insulator field effect transistor with heterojunction gate
    3.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权

    公开(公告)号：US07105421B1

    公开(公告)日：2006-09-12

    申请号：US10835438

    申请日：2004-04-29

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    Method of forming an electroless nucleation layer on a via bottom
    4.
    发明授权
    Method of forming an electroless nucleation layer on a via bottom 有权
    在通孔底部形成无电解成核层的方法

    公开(公告)号：US06815340B1

    公开(公告)日：2004-11-09

    申请号：US10145928

    申请日：2002-05-15

    申请人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

    发明人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76874

    摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.

    摘要翻译： 制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物， 以及使用合金在导电层的暴露部分上形成成核层。 成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。

    Silicon on insulator field effect transistor with heterojunction gate
    6.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权
    具有异质结栅的绝缘体上的场效应晶体管

    公开(公告)号：US06759308B2

    公开(公告)日：2004-07-06

    申请号：US09902429

    申请日：2001-07-10

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2130

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    摘要翻译： 在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。 沟道区域被轻掺杂第一杂质以增加第一类型的自由载流子导电性。 源极区和漏极区是具有第一杂质的重掺杂物。 栅极和背栅极沿着沟道区域的侧面定位并且从源极区域延伸并且注入具有大于硅的能隙的第二半导体，并且注入杂质以增加第二类型的自由载流子 。

    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process
    8.
    发明授权
    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process 有权
    具有用于CMOS器件的注入掺杂剂的PVD非晶硅层的金属栅极和用替代栅极工艺制造的方法

    公开(公告)号：US06589866B1

    公开(公告)日：2003-07-08

    申请号：US09691226

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2144

    CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L29/4933

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 然后在PVD非晶硅层上形成金属。 另外的掺杂剂被注入到PVD非晶硅层中。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

    Linerless shallow trench isolation method
    9.
    发明授权
    Linerless shallow trench isolation method 失效
    无缝浅沟隔离法

    公开(公告)号：US06534379B1

    公开(公告)日：2003-03-18

    申请号：US10051698

    申请日：2002-01-18

    申请人： Philip Fisher ,  Ming-Ren Lin ,  Matthew S. Buynoski

    发明人： Philip Fisher ,  Ming-Ren Lin ,  Matthew S. Buynoski

    IPC分类号： H01L2176

    CPC分类号： H01L21/76264 ,  H01L21/76283

    摘要： A method of making a semiconductor device and a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; forming an isolation trench, the isolation trench defining an active island in the silicon active layer; rounding at least one corner in the active island by application of a high RF bias power high density plasma; and filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma. In one embodiment, the rounding step comprises application of a HDP under etching conditions, and the filling step comprises application of a HDP under deposition conditions.

    摘要翻译： 一种制造半导体器件的方法以及在绝缘体上硅半导体器件上隔离有源岛的方法，包括以下步骤：提供具有硅有源层，介电隔离层和绝缘体隔离层的绝缘体上半导体晶片， 在硅衬底上形成硅介质隔离层上的硅有源层和电介质隔离层的硅衬底; 形成隔离沟槽，所述隔离沟槽在所述硅有源层中限定有源岛; 通过应用高RF偏置功率的高密度等离子体使活动岛中的至少一个角落四舍五入; 以及通过施加低RF偏置功率的高密度等离子体，用绝缘沟槽隔离材料填充隔离沟槽。 在一个实施例中，舍入步骤包括在蚀刻条件下施加HDP，并且填充步骤包括在沉积条件下施加HDP。

    Doping of thin amorphous silicon work function control layers of MOS gate electrodes
    10.
    发明授权
    Doping of thin amorphous silicon work function control layers of MOS gate electrodes 有权
    掺杂MOS栅电极薄的非晶硅功函数控制层

    公开(公告)号：US06518113B1

    公开(公告)日：2003-02-11

    申请号：US09776853

    申请日：2001-02-06

    申请人： Matthew S. Buynoski

    发明人： Matthew S. Buynoski

    IPC分类号： H01L218238

    CPC分类号： H01L21/823842 ,  Y10S438/923

    摘要： Work function control layers are provided in in-laid, metal gate electrode, Si-based MOS transistors and CMOS devices by a process which avoids deleterious dopant implantation processing resulting in damage to the thin gate insulator layer and undesirable doping of the underlying channel region. According to the invention, an amorphous Si layer is formed over the thin gate insulator layer by a low energy deposition process which does not adversely affect the gate insulator layer and subsequently doped by means of another low energy process, e.g., low sheath voltage plasma doping, which does not damage the gate insulator layer or dope the underlying channel region of the Si-based substrate. Subsequent thermal processing during device manufacture results in activation of the dopant species and conversion of the a-Si layer to a doped polycrystalline Si layer of substantially increased electrical conductivity.

    摘要翻译： 工作功能控制层通过一种避免有害的掺杂剂注入处理导致薄栅极绝缘体层的损坏和对下面的沟道区的不期望的掺杂的过程提供在嵌入式金属栅电极，Si基MOS晶体管和CMOS器件中。 根据本发明，通过低能量沉积工艺在薄栅极绝缘体层上形成非晶Si层，该方法不会对栅极绝缘体层产生不​​利影响，并且随后通过另一种低能量工艺（例如，低鞘电压等离子体掺杂 ，其不损坏栅极绝缘体层或掺杂Si基衬底的下面的沟道区域。 在器件制造过程中随后的热处理导致掺杂剂物质的激活和a-Si层转变成具有显着增加的导电性的掺杂多晶Si层。