公开(公告)号：US06387750B1

公开(公告)日：2002-05-14

申请号：US09895389

申请日：2001-07-02

申请人： Erh-Kun Lai ,  Shou-Wei Hwang ,  Jiann-Jen Chiou ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Shou-Wei Hwang ,  Jiann-Jen Chiou ,  Yu-Ping Huang

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L27/0805 ,  H01L29/66181

摘要： A method of forming a metal-insulator-metal (MIM) capacitor is disclosed. The method provides a three dimensional MIM capacitor having upgraded capacitance. A plurality of trenches are formed within the MIM capacitor to increase the charge storage area of the MIM capacitor without occupying additional planar area thereby upgrade the capacitance of the MIM capacitor and the integration.

摘要翻译： 公开了一种形成金属 - 绝缘体 - 金属（MIM）电容器的方法。 该方法提供具有升级电容的三维MIM电容器。 在MIM电容器内形成多个沟槽，以增加MIM电容器的电荷存储区域，而不占用额外的平面区域，从而升高MIM电容器的电容和集成度。

公开(公告)号：US06482738B1

公开(公告)日：2002-11-19

申请号：US09996821

申请日：2001-11-30

申请人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/115 ,  H01L29/665 ,  H01L29/6656

摘要： The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of present invention achieve above objectives by principally using a design rule to adequately arrange elements in proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is previously formed in the spaced region between the two neighboring memory cells and is used as a mask. Thus, in a following selective etching process, a part of silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objectives is achieved.

摘要翻译： 本发明主要提供一种在积分电路上局部形成金属硅化物的方法，并且避免由同一字线上的存储单元之间形成的金属硅化物引起的漏电流的现象。 本发明的方法通过主要使用设计规则来适当地排列适当距离的元件来达到上述目的。 在一个实施例中，为了在积分电路上形成金属硅化物层并且避免在相同字线上的两个相邻存储器单元之间形成的金属硅化物，预先在两个相邻存储器单元之间的间隔区域中形成电介质层，并且是 用作面具。 因此，在随后的选择性蚀刻工艺中，上述间隔区域内的硅衬底的一部分可被保护而不被暴露。 因此，在间隔区域中不形成金属硅化物，实现上述目的。

公开(公告)号：US06468867B1

公开(公告)日：2002-10-22

申请号：US09916267

申请日：2001-07-30

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L218234

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氮化物层作为掩模层，以在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06372640B1

公开(公告)日：2002-04-16

申请号：US09917645

申请日：2001-07-31

申请人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L27/10873 ,  H01L29/665

摘要： The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.

摘要翻译： 本发明主要提供一种在积分电路上局部形成金属硅化物的方法，并避免由同一字线上的存储单元之间形成的金属硅化物引起的漏电流的现象。本发明的方法实现了上述 目标主要是使用设计规则来适当地排列适当距离的元素。 在一个实施例中，为了在积分电路上形成金属硅化物层，并且避免在相同字线上的两个相邻存储器单元之间形成金属硅化物，首先在两个相邻存储器单元之间的间隔区域中形成介电层，以形成 用作面具。 因此，在随后的选择性蚀刻工艺中，上述间隔区域内的硅衬底的一部分可被保护而不被暴露。 因此，在间隔区域中不形成金属硅化物，实现上述目的。

公开(公告)号：US06383903B1

公开(公告)日：2002-05-07

申请号：US09918638

申请日：2001-08-01

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L213205

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/1052

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氧化物层作为掩模层，在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06548406B2

公开(公告)日：2003-04-15

申请号：US09930998

申请日：2001-08-17

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L21302

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L29/66833

摘要： A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

摘要翻译： 公开了一种形成具有金属氧化物氮化物半导体（MONOS）存储器和混合信号电路的集成电路的方法。 本发明将诸如MONOS器件的非易失性存储器件和诸如MOS器件的逻辑器件以及PIP电容器集成到具有减少的工艺步骤的SOC器件中。

公开(公告)号：US06566225B2

公开(公告)日：2003-05-20

申请号：US09921580

申请日：2001-08-06

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Yu-Ping Huang

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

摘要翻译： 本发明提供一种沟槽结构的形成方法，包括在衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成第一多晶硅层，在其上形成氧化物层。 在氧化物层上形成第二多晶硅层。 去除部分第二多晶硅层，氧化物层，第一多晶硅层和衬垫氧化物层以暴露部分衬底。 蚀刻第二多晶硅层和部分衬底以在衬底中形成沟槽结构。 沟槽结构的蚀刻深度由第二多晶硅层的蚀刻厚度很好地控制。

公开(公告)号：US06355539B1

公开(公告)日：2002-03-12

申请号：US09849245

申请日：2001-05-07

申请人： Erh-Kun Lai ,  Shou-Wei Huang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Shou-Wei Huang ,  Yu-Ping Huang

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method for forming a shallow trench isolation is disclosed. The method avoids using any silicon nitride material to prevent the kooi effect and use spacers to protect the corner portions of the STI. A conductive layer is used to replace the conventional used silicon nitride layer in the formation of conventional STI regions. The invention also uses a dielectric layer comprising a pad oxide layer as a sacrificial oxide layer so that an additional sacrificial oxide layer is no longer needed. The conductive layer will be oxidized together with the substrate in the formation of the gate oxide layer so that the isolation quality will not be degraded.

摘要翻译： 公开了一种用于形成浅沟槽隔离的方法。 该方法避免使用任何氮化硅材料来防止kooi效应并使用间隔物来保护STI的拐角部分。 在传统的STI区域的形成中，使用导电层代替常规使用的氮化硅层。 本发明还使用包括衬垫氧化物层作为牺牲氧化物层的电介质层，使得不再需要额外的牺牲氧化物层。 在形成栅极氧化物层时，导电层将与衬底一起被氧化，使得隔离质量不会降低。

公开(公告)号：US09018615B2

公开(公告)日：2015-04-28

申请号：US11833563

申请日：2007-08-03

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00 ,  H01L45/00

CPC分类号： H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144

摘要： A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.

摘要翻译： 包括能够通过施加能量在电性能状态之间切换的存储材料的存储单元装置包括第一和第二电极，与第二电极电接触的存储材料（例如相变材料）插头 以及由电介质形式支撑并与第一电极和记忆材料塞电接触的导电膜。 电介质形式在第一电极附近较宽，在相变插头附近较窄。 导电膜与相变插塞的接触面积部分地由形成导电膜的电介质形状的几何形状限定。 此外，制造该器件的方法包括在第一电极上构建电介质形式，以及在电介质形式上形成导电膜的步骤。

公开(公告)号：US08587983B2

公开(公告)日：2013-11-19

申请号：US13281266

申请日：2011-10-25

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L45/00

CPC分类号： H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625

摘要： A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

摘要翻译： 描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。 电介质构件，例如 底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。 底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。 用于构造底部电介质构件的一种合适的材料是氧化硅。 双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。 附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。 顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。