公开(公告)号：US08837886B2

公开(公告)日：2014-09-16

申请号：US13054968

申请日：2009-08-06

申请人： Yutaka Hoshino ,  Masayoshi Tsukamoto ,  Koichi Mizuno ,  Eiji Konda ,  Keiichiro Sugimoto ,  Shinichi Niwa

发明人： Yutaka Hoshino ,  Masayoshi Tsukamoto ,  Koichi Mizuno ,  Eiji Konda ,  Keiichiro Sugimoto ,  Shinichi Niwa

IPC分类号： G02B6/44

CPC分类号： G02B6/443 ,  G02B6/4402

摘要： An optical fiber cable which is suitably set in a conduit by pushing the optical fiber cable into the conduit so as to insert the optical fiber cable through the conduit and which does not reduce the ease of manufacture and the mechanical characteristics of the optical fiber cable. The optical fiber cable includes an optical fiber cable core wire and a sheath covering the optical fiber cable core wire, wherein a dynamic friction coefficient between a surface of the sheath of the optical fiber cable and a surface of a sheath of another optical fiber cable is 0.17 to 0.34, and a dynamic friction coefficient between the surface of the sheath of the optical fiber cable and a surface of a sheet composed of polyvinyl chloride is 0.30 to 0.40.

摘要翻译： 一种光缆，其通过将光纤电缆推入导管中适当地设置在导管中，以便将光纤电缆插入导管中，并且不会降低光纤电缆的制造容易性和机械特性。 光缆包括光纤电缆芯线和覆盖光缆芯线的护套，其中光纤电缆护套的表面与另一光纤电缆护套表面之间的动摩擦系数为 0.17〜0.34，光缆的护套表面和由聚氯乙烯构成的片的表面之间的动摩擦系数为0.30〜0.40。

公开(公告)号：US20120133431A1

公开(公告)日：2012-05-31

申请号：US13367121

申请日：2012-02-06

申请人： Tsuyoshi KAWAKAMI ,  Akihiko FURUKAWA ,  Satoshi YAMAKAWA ,  Tetsuya IIDA ,  Masao KONDO ,  Yutaka HOSHINO

发明人： Tsuyoshi KAWAKAMI ,  Akihiko FURUKAWA ,  Satoshi YAMAKAWA ,  Tetsuya IIDA ,  Masao KONDO ,  Yutaka HOSHINO

IPC分类号： H03F3/45

CPC分类号： H03F3/211 ,  H03F1/56 ,  H03F3/26 ,  H03F2200/537 ,  H03F2203/21139

摘要： In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

摘要翻译： 为了实现功率放大电路的频率特性的更宽的带宽，通过二次电感器将分别以不同频率匹配的差分推挽放大器的输出组合在一起，并且输出组合信号。

公开(公告)号：US20110278581A1

公开(公告)日：2011-11-17

申请号：US13094915

申请日：2011-04-27

申请人： Komaki INOUE ,  Yutaka HOSHINO

发明人： Komaki INOUE ,  Yutaka HOSHINO

IPC分类号： H01L29/04 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.

摘要翻译： 提高了在SOI衬底上形成的MOSFET的半导体器件的可靠性。 半导体器件的制造方法简化。 在SOI衬底SB上形成的具有n沟道MOSFET Qn的半导体器件包括在BOX膜下形成为在支撑衬底的上表面上的扩散层的n +型半导体区域，以及与n + 并且穿透可以控制支撑衬底的电位的元件隔离区域。 在SOI衬底SB的平面上，n沟道MOSFETsn各自沿第一方向延伸，并且布置在沿第一方向彼此相邻形成的接触插头CT2之间。

公开(公告)号：US20110255834A1

公开(公告)日：2011-10-20

申请号：US13142163

申请日：2009-12-24

申请人： Masayoshi Tsukamoto ,  Yutaka Hoshino ,  Noboru Okada

发明人： Masayoshi Tsukamoto ,  Yutaka Hoshino ,  Noboru Okada

IPC分类号： G02B6/44

CPC分类号： G02B6/4402 ,  G02B6/4433

摘要： An optical fiber cable enabling further reduction of possibilities of disconnection of optical fiber due to, for instance, cicada oviposition. The optical fiber cable (10) is provided with: an optical fiber core (1); a tension member (2), which is arranged in parallel to the optical fiber core (1) on one side or on the both sides of the optical fiber core (1); and a sheath (3) which integrally covers the optical fiber core (1) and the tension member (2). At least one portion of the sheath (3) is composed of a polymeric material having a yield point stress of 12 MPa or higher.

摘要翻译： 一种光纤电缆，能够进一步降低由于例如蝉产卵而导致的光纤断开的可能性。 光缆（10）设有：光纤芯（1）; 张力构件（2），其在所述光纤芯（1）的一侧或两侧平行于所述光纤芯（1）布置; 以及一体地覆盖光纤芯（1）和张紧构件（2）的护套（3）。 护套（3）的至少一部分由屈服点应力为12MPa以上的聚合物材料构成。

公开(公告)号：US20110254087A1

公开(公告)日：2011-10-20

申请号：US13167850

申请日：2011-06-24

申请人： Tomoyuki MIYAKE ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Makoto Hatori

发明人： Tomoyuki MIYAKE ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Makoto Hatori

IPC分类号： H01L29/10

CPC分类号： H01L29/66659 ,  H01L21/823425 ,  H01L23/3677 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/7835 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n− type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.

摘要翻译： 为了减小尺寸并提高具有由硅功率MOSFET组成的放大器元件的RF功率模块的功率附加效率，传统上处于折衷关系的导通电阻和反馈电容通过形成结构 存在于功率MOSFET的栅极电极和n +型漏极区域之间的偏移漏极区域，成为双偏移漏极区域。 更具体地说，这是通过将最接近栅电极的n型偏移漏极区域的杂质浓度调整为相对较低而调整n型偏移漏极区域的杂质浓度来实现的，该杂质浓度远离 栅电极，要比较高。

公开(公告)号：US20110220999A1

公开(公告)日：2011-09-15

申请号：US13111001

申请日：2011-05-19

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。 连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

公开(公告)号：US20100001329A1

公开(公告)日：2010-01-07

申请号：US12559274

申请日：2009-09-14

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L27/11 ,  H01L27/108

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US20090224318A1

公开(公告)日：2009-09-10

申请号：US12412128

申请日：2009-03-26

申请人： Makoto Hatori ,  Yutaka Hoshino

发明人： Makoto Hatori ,  Yutaka Hoshino

IPC分类号： H01L29/78

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/66659 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n−-type offset drain region, an n-type offset drain region, and an n+-type drain region. A side wall spacer comprising a silicon film is formed via an insulating film on the side wall of the gate electrode over the drain side thereof, and a field plate electrode is formed by this side wall spacer. The field plate electrode does not extend above the gate electrode, and a metal silicide film is formed over the entire upper surface of the gate electrode in the silicide process.

摘要翻译： 本发明改进了半导体器件的性能。 金属硅化物膜通过硅化物工艺在LDMOSFET的栅电极和n +型源极区上形成，并且在n型偏移漏极区域，n型偏移漏极区域上不形成这种金属硅化物膜 ，和n +型漏极区域。 通过绝缘膜在其漏极侧的栅电极的侧壁上形成包括硅膜的侧壁隔片，并且通过该侧壁间隔物形成场板电极。 场板电极不在栅电极上方延伸，并且在硅化物工艺中在栅电极的整个上表面上形成金属硅化物膜。

公开(公告)号：US20070194407A1

公开(公告)日：2007-08-23

申请号：US11783779

申请日：2007-04-12

申请人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H01L29/00

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

摘要翻译： 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US07199433B2

公开(公告)日：2007-04-03

申请号：US10756305

申请日：2004-01-14

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L27/108

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。