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公开(公告)号：US20220140837A1
公开(公告)日：2022-05-05
申请号：US17397303
申请日：2021-08-09
发明人： Danfeng Xu
摘要： A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.
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公开(公告)号：US10720936B1
公开(公告)日：2020-07-21
申请号：US16518504
申请日：2019-07-22
发明人： Danfeng Xu
摘要： A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.
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公开(公告)号：US09705531B2
公开(公告)日：2017-07-11
申请号：US14624872
申请日：2015-02-18
发明人： Kai Keung Chan , Yu Kou , Tze Yin Cheung , Danfeng Xu
CPC分类号： H03M13/3961 , H03M13/4107 , H03M13/4161 , H03M13/6508
摘要： A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.
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公开(公告)号：US09742422B2
公开(公告)日：2017-08-22
申请号：US15183723
申请日：2016-06-15
发明人： Danfeng Xu , Kai Keung Chan , Yu Kou
CPC分类号： H03M1/1023 , H03M1/1061 , H03M1/1245 , H03M1/34 , H03M1/36 , H03M1/363
摘要： A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.
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5.发明申请TIMING RECOVERY FOR DIGITAL RECEIVER WITH INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS 有权数字接收机的时序恢复与交互式模数转换器公开(公告)号：US20170012630A1
公开(公告)日：2017-01-12
申请号：US15271096
申请日：2016-09-20
发明人： Yu Kou
CPC分类号： H03L7/0807 , H03L7/091 , H03L7/093 , H03L7/146 , H03M1/0624 , H03M1/1215 , H04L7/0016 , H04L7/0062 , H04L7/0079 , H04L7/0331
摘要： A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.
摘要翻译： 具有模数转换器的接收器，具有相位可调采样时钟。 第一模数转换器在第一采样时钟的控制下将模拟信号转换成第一数字样本。 第一时钟发生器基于至少一个第一相位控制信号来调节第一采样时钟的相位。 第二模数转换器在第二采样时钟的控制下将模拟信号转换成第二数字采样。 第二时钟发生器基于至少一个第二相位控制信号调整第二采样时钟的相位。 数据判定电路基于第一和第二采样来恢复数据。 反馈电路接收恢复的数据并产生用于第一时钟发生器的至少一个第一相位控制信号，并且基于第一相位控制信号产生用于第二时钟发生器的至少一个第二相位控制信号。
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公开(公告)号：US20160301420A1
公开(公告)日：2016-10-13
申请号：US15183723
申请日：2016-06-15
发明人： Danfeng Xu , Kai Keung Chan , Yu Kou
CPC分类号： H03M1/1023 , H03M1/1061 , H03M1/1245 , H03M1/34 , H03M1/36 , H03M1/363
摘要： A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.
摘要翻译： 具有可调参考电压的模数转换器的接收机，其被校准以考虑过程变化。 接收机包括模数转换器。 模数转换器包括用于产生一组N个参考电压的参考发生器。 参考发生器基于一个或多个控制信号来调节该组N个参考电压的电压电平。 多个比较器将输入信号与N个参考电压的组进行比较。 校准电路根据比较器的输出产生用于调整N个参考电压的电压电平的一个或多个控制信号。
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公开(公告)号：US20160241274A1
公开(公告)日：2016-08-18
申请号：US14624872
申请日：2015-02-18
发明人： Kai Keung Chan , Yu Kou , Tze Yin Cheung , Danfeng Xu
CPC分类号： H03M13/3961 , H03M13/4107 , H03M13/4161 , H03M13/6508
摘要： A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.
摘要翻译： 支持不同解码模式的多模式维特比解码器。 维特比解码器包括用于输出一个或多个数据符号值的电路。 电路将第一解码模式（例如，PAM-4）中的一个或多个数据符号值设置为第一数量的单位间隔。 电路在第二解码模式（例如NRZ）中将一个或多个数据符号值设置为第二数量的单位间隔。 单位间隔的第二数量大于第一单位间隔数量。 分支度量电路适于在第一解码模式中，基于第一数量单位间隔的数据符号值生成一组维特比分支度量。 分支度量电路适于在第二解码模式中，基于第二数量单位间隔的数据符号值生成维特比分支量度集合。
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8.发明申请公开(公告)号：US20160173271A1
公开(公告)日：2016-06-16
申请号：US14572676
申请日：2014-12-16
发明人： Yu Kou
CPC分类号： H04L7/0029 , H04L7/0062 , H04L7/04
摘要： A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.
摘要翻译： 用于高速通信的接收机。 该接收器包括模数转换器，用于在由采样时钟控制的定时处将模拟输入信号转换成至少一个数字输入信号。 有限脉冲响应滤波器基于数字输入信号产生至少一个滤波输入信号。 数据判定电路根据经滤波的输入信号恢复数据。 经过滤波的输入信号和恢复的数据可以提供给反馈回路，以确定采样时钟的定时误差，然后采样时钟用于产生采样时钟。
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公开(公告)号：US10931295B2
公开(公告)日：2021-02-23
申请号：US16902919
申请日：2020-06-16
发明人： Danfeng Xu
摘要： A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.
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公开(公告)号：US20210028791A1
公开(公告)日：2021-01-28
申请号：US16902919
申请日：2020-06-16
发明人： Danfeng Xu
摘要： A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.
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