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公开(公告)号：US20180108106A1
公开(公告)日：2018-04-19
申请号：US15298026
申请日：2016-10-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Angel E. Socarras
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T15/80
Abstract: A GPU stores resource allocations for a plurality of shaders to process processing a graphics workload, and applies those stored resource allocations when the same or a similar graphics workload is received subsequently by the GPU. In response to receiving a new graphics workload with a given unique identifier for the first time, the GPU employs a series of performance monitors to measure performance characteristics for processing the workload. The GPU then calculates a resource allocation for the workload based on the performance characteristics, and stores the resource allocation. In response to subsequently receiving a previously stored graphics workload with the given identifier, the GPU retrieves the stored resource allocation for the graphics workload, and applies the resource allocation for processing the graphics workload.
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公开(公告)号：US20180082398A1
公开(公告)日：2018-03-22
申请号：US15270679
申请日：2016-09-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Fuad Ashkar , Harry J. Wise , Rex Eldon McCrary , Angel E. Socarras
CPC classification number: G06T1/20 , G06F1/325 , G06F3/0604 , G06F3/0638 , G06F3/0685 , G06T1/60
Abstract: An adaptive list stores previously received hardware state information that has been used to configure a graphics processing core. One or more filters are configured to filter packets from a packet stream directed to the graphics processing core. The packets are filtered based on a comparison of hardware state information included in the packet and hardware state information stored in the adaptive list. The adaptive list is modified in response to filtering the first packet. The filters can include a hardware filter and a software filter that selectively filters the packets based on whether the graphics processing core is limiting throughput. The adaptive list can be implemented as content-addressable memory (CAM), a cache, or a linked list.
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公开(公告)号：US10861122B2
公开(公告)日：2020-12-08
申请号：US15156658
申请日：2016-05-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
Abstract: Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.
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4.发明申请公开(公告)号：US20180121386A1
公开(公告)日：2018-05-03
申请号：US15354560
申请日：2016-11-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Angel E. Socarras , Michael Mantor , YunXiao Zou , Bin He
IPC: G06F15/80 , G06F9/30 , G06F12/0875 , G06F12/0891
CPC classification number: G06F15/8007 , G06F9/3001 , G06F9/30105 , G06F9/3012 , G06F9/30123 , G06F9/3828 , G06F9/3851 , G06F9/3887 , G06F9/3891 , G06F12/0875 , G06F12/0891 , G06F2212/604
Abstract: A super single instruction, multiple data (SIMD) computing structure and a method of executing instructions in the super-SIMD is disclosed. The super-SIMD structure is capable of executing more than one instruction from a single or multiple thread and includes a plurality of vector general purpose registers (VGPRs), a first arithmetic logic unit (ALU), the first ALU coupled to the plurality of VGPRs, a second ALU, the second ALU coupled to the plurality of VGPRs, and a destination cache (Do$) that is coupled via bypass and forwarding logic to the first ALU, the second ALU and receiving an output of the first ALU and the second ALU. The Do$ holds multiple instructions results to extend an operand by-pass network to save read and write transactions power. A compute unit (CU) and a small CU including a plurality of super-SIMDs are also disclosed.
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公开(公告)号：US09720486B2
公开(公告)日：2017-08-01
申请号：US14865928
申请日：2015-09-25
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Angel E. Socarras , Fei Guo
CPC classification number: G06F1/324 , G06F1/06 , G06F1/10 , G06F1/3243 , Y02D10/126 , Y02D10/152
Abstract: A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.
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Patent Agency Ranking
公开(公告)号：US20160260192A1
公开(公告)日：2016-09-08
申请号：US15156658
申请日：2016-05-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
CPC classification number: G06T1/20 , G06T1/60 , G09G5/363 , G09G2360/06
Abstract: Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.
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7.发明申请SYSTEM AND METHOD OF TESTING PROCESSOR UNITS USING CACHE RESIDENT TESTING 审中-公开使用高速缓存测试测试处理器单元的系统和方法公开(公告)号：US20150286573A1
公开(公告)日：2015-10-08
申请号：US14243050
申请日：2014-04-02
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Angel E. Socarras , Kostantinos Danny Christidis , Curtis Alan Gilgan , Alexander Fuad Ashkar
IPC: G06F12/08
CPC classification number: G06F12/0875 , G06F11/2236 , G06F11/2733 , G06F11/3037 , G06F2212/452 , G06F2212/62
Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.
Abstract translation: 公开了装置，计算机可读介质和使用高速缓存驻留测试的处理器单元测试的方法。 该方法可以包括将测试程序加载到包括一个或多个处理器单元的芯片上的高速缓存中。 该方法可以包括执行测试程序以生成一个或多个结果的一个或多个处理器单元。 该方法可以包括将第一存储器引用重定向到高速缓存，其中在执行测试程序期间生成第一存储器引用。 该方法可以包括确定一个或多个生成的结果是否匹配一个或多个测试结果。 如果存储器请求包括不驻留在高速缓存中的存储器位置，则该方法可以包括将存储器请求重定向到驻留在高速缓存中的存储器位置。 如果存储器请求没有被指向高速缓存，则该方法可以包括将存储器请求重定向到高速缓存。
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公开(公告)号：US11494192B2
公开(公告)日：2022-11-08
申请号：US16860842
申请日：2020-04-28
Inventor： Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
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公开(公告)号：US20210090208A1
公开(公告)日：2021-03-25
申请号：US17113827
申请日：2020-12-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
Abstract: Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.
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公开(公告)号：US10656951B2
公开(公告)日：2020-05-19
申请号：US15789318
申请日：2017-10-20
Inventor： Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
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