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公开(公告)号：US09192052B2
公开(公告)日：2015-11-17
申请号：US14515806
申请日：2014-10-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Ravi B. Bingi , Ranger H. Lam , Jason R. Talbert , Pravind K. Hurry , Brian E. Longhenry , Andrew W. Steinbach , Jeff H. Gruger
CPC classification number: H05K3/10 , G06F13/409 , H05K1/11 , Y10T29/49124 , Y10T29/49155
Abstract: An apparatus includes a printed circuit board including a connector footprint comprising a first footprint portion operative to receive a first connector portion and a second footprint portion operative to receive a second connector portion. The first footprint portion is compliant with a first communications link type and the first and second footprint portions are jointly compliant with a second communications link type. The printed circuit board includes first conductive traces coupled to the first footprint portion and a first device footprint. The first conductive traces are selectively configurable according to a selected one of the first and second communications link types. The printed circuit board includes a second conductive traces coupled to the second footprint portion and the first device footprint. in at least one embodiment of the apparatus, the first communications link type is AC-coupled and the second communications link type is DC-coupled.
Abstract translation: 一种装置包括印刷电路板，该印刷电路板包括连接器覆盖区，其包括用于接收第一连接器部分的第一覆盖区域和用于接收第二连接器部分的第二覆盖区域。 第一足迹部分符合第一通信链路类型，并且第一和第二覆盖部分共同符合第二通信链路类型。 印刷电路板包括耦合到第一覆盖区部分的第一导电迹线和第一器件覆盖区。 根据所选择的第一和第二通信链路类型中的一个，可以选择性地配置第一导电迹线。 印刷电路板包括耦合到第二封装部分和第一器件覆盖区的第二导电迹线。 在装置的至少一个实施例中，第一通信链路类型是AC耦合的，并且第二通信链路类型是DC耦合的。
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公开(公告)号：US11657014B2
公开(公告)日：2023-05-23
申请号：US17115384
申请日：2020-12-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Jason R. Talbert
IPC: G06F13/40 , G06F13/20 , G06F9/4401
CPC classification number: G06F13/4027 , G06F13/20 , G06F9/4405 , G06F2213/40
Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.
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公开(公告)号：US20150034363A1
公开(公告)日：2015-02-05
申请号：US14515806
申请日：2014-10-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Ravi B. Bingi , Ranger H. Lam , Jason R. Talbert , Pravind K. Hurry , Brian E. Longhenry , Andrew W. Steinbach , Jeff H. Gruger
CPC classification number: H05K3/10 , G06F13/409 , H05K1/11 , Y10T29/49124 , Y10T29/49155
Abstract: An apparatus includes a printed circuit board including a connector footprint comprising a first footprint portion operative to receive a first connector portion and a second footprint portion operative to receive a second connector portion. The first footprint portion is compliant with a first communications link type and the first and second footprint portions are jointly compliant with a second communications link type. The printed circuit board includes first conductive traces coupled to the first footprint portion and a first device footprint. The first conductive traces are selectively configurable according to a selected one of the first and second communications link types. The printed circuit board includes a second conductive traces coupled to the second footprint portion and the first device footprint. in at least one embodiment of the apparatus, the first communications link type is AC-coupled and the second communications link type is DC-coupled.
Abstract translation: 一种装置包括印刷电路板，该印刷电路板包括连接器覆盖区，其包括用于接收第一连接器部分的第一覆盖区域和用于接收第二连接器部分的第二覆盖区域。 第一足迹部分符合第一通信链路类型，并且第一和第二覆盖部分共同符合第二通信链路类型。 印刷电路板包括耦合到第一覆盖区部分的第一导电迹线和第一器件覆盖区。 根据所选择的第一和第二通信链路类型中的一个，可以选择性地配置第一导电迹线。 印刷电路板包括耦合到第二封装部分和第一器件覆盖区的第二导电迹线。 在装置的至少一个实施例中，第一通信链路类型是AC耦合的，并且第二通信链路类型是DC耦合的。
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公开(公告)号：US12007928B2
公开(公告)日：2024-06-11
申请号：US18322183
申请日：2023-05-23
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Jason R. Talbert
IPC: G06F13/40 , G06F13/20 , G06F9/4401
CPC classification number: G06F13/4027 , G06F13/20 , G06F9/4405 , G06F2213/40
Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.
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