公开(公告)号：US10223124B2

公开(公告)日：2019-03-05

申请号：US13739161

申请日：2013-01-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Ramkumar Jayaseelan ,  Ravindra N Bhargava

IPC: G06F9/00 ,  G06F9/38

Abstract: A processor employs one or more branch predictors to issue branch predictions for each thread executing at an instruction pipeline. Based on the branch predictions, the processor determines a branch prediction confidence for each of the executing threads, whereby a lower confidence level indicates a smaller likelihood that the corresponding thread will actually take the predicted branch. Because speculative execution of an untaken branch wastes resources of the instruction pipeline, the processor prioritizes threads associated with a higher confidence level for selection at the stages of the instruction pipeline.

公开(公告)号：US20140297965A1

公开(公告)日：2014-10-02

申请号：US13854541

申请日：2013-04-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ramkumar Jayaseelan ,  John Kalamatianos

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/528 ,  G06F11/366 ,  G06F12/0215 ,  G06F12/0891

Abstract: A processor employs a prefetch prediction module that predicts, for each prefetch request, whether the prefetch request is likely to be satisfied from (“hit”) the cache. The arbitration priority of prefetch requests that are predicted to hit the cache is reduced relative to demand requests or other prefetch requests that are predicted to miss in the cache. Accordingly, an arbiter for the cache is less likely to select prefetch requests that hit the cache, thereby improving processor throughput.

Abstract translation: 处理器采用预取预测模块，其针对每个预取请求预测预取请求是否可能从缓存（“命中”）满足。 预测到达高速缓存的预取请求的仲裁优先级相对于预期在高速缓存中丢失的请求请求或其他预取请求而减少。 因此，缓存的仲裁器不太可能选择命中高速缓存的预取请求，从而提高处理器的吞吐量。

公开(公告)号：US20160077565A1

公开(公告)日：2016-03-17

申请号：US14489138

申请日：2014-09-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ramkumar Jayaseelan

IPC: G06F1/28 ,  G06F9/54

CPC classification number: G06F9/546 ,  G06F1/324 ,  G06F1/3243 ,  G06F5/06 ,  Y02D10/126 ,  Y02D10/152

Abstract: A processing device includes one or more queues to convey data between a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A system management unit configures a first operating frequency of the producing processor unit and a second operating frequency of the consuming processor unit based on a power constraint for the processing device and a target size of the one or more queues.

Abstract translation: 处理设备包括一个或多个队列，用于在第一定时域中的产生处理器单元和与第一定时域异步的第二定时域中的消费处理器单元之间传送数据。 系统管理单元基于处理设备的功率约束和一个或多个队列的目标大小来配置生产处理器单元的第一工作频率和消耗处理器单元的第二工作频率。

公开(公告)号：US20140297996A1

公开(公告)日：2014-10-02

申请号：US13854171

申请日：2013-04-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ramkumar Jayaseelan

IPC: G06F9/38

CPC classification number: G06F9/3848

Abstract: A processor includes storage elements to store a first and second value, as well as a plurality of hash units coupled to the storage elements. Each hash unit performs a hash operation using the first value and the second value to generate a corresponding hash result value. The processor further includes selection logic to select a hash result value from the hash result values generated by the plurality of hash units responsive to a selection input generated from another hash operation performed using the first value and the second value. A method includes predicting whether a branch instruction is taken based on a prediction value stored at an entry of a branch prediction table indexed by an index value selected from a plurality of values concurrently generated from an address value of the branch instruction and a branch history value representing a history of branch directions at the processor.

Abstract translation: 处理器包括用于存储第一和第二值的存储元件以及耦合到存储元件的多个散列单元。 每个散列单元使用第一值和第二值来执行散列操作，以产生相应的散列结果值。 处理器还包括选择逻辑，用于响应于从使用第一值和第二值执行的另一散列操作生成的选择输入，从由多个散列单元产生的散列结果值中选择散列结果值。 一种方法包括：基于存储在由从由分支指令的地址值同时产生的多个值中选择的索引值索引的分支预测表的条目中存储的预测值，以及分支历史值 代表处理器处的分支方向的历史。

公开(公告)号：US09223705B2

公开(公告)日：2015-12-29

申请号：US13854541

申请日：2013-04-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Ramkumar Jayaseelan ,  John Kalamatianos

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/02 ,  G06F9/52 ,  G06F11/36

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/528 ,  G06F11/366 ,  G06F12/0215 ,  G06F12/0891

Abstract: A processor employs a prefetch prediction module that predicts, for each prefetch request, whether the prefetch request is likely to be satisfied from (“hit”) the cache. The arbitration priority of prefetch requests that are predicted to hit the cache is reduced relative to demand requests or other prefetch requests that are predicted to miss in the cache. Accordingly, an arbiter for the cache is less likely to select prefetch requests that hit the cache, thereby improving processor throughput.

Abstract translation: 处理器采用预取预测模块，其针对每个预取请求预测预取请求是否可能从缓存（“命中”）满足。 预测到达高速缓存的预取请求的仲裁优先级相对于预期在高速缓存中丢失的请求请求或其他预取请求而减少。 因此，缓存的仲裁器不太可能选择命中高速缓存的预取请求，从而提高处理器的吞吐量。

公开(公告)号：US20140201507A1

公开(公告)日：2014-07-17

申请号：US13739161

申请日：2013-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ramkumar Jayaseelan ,  Ravindra N. Bhargava

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3848 ,  G06F9/3851

Abstract: A processor employs one or more branch predictors to issue branch predictions for each thread executing at an instruction pipeline. Based on the branch predictions, the processor determines a branch prediction confidence for each of the executing threads, whereby a lower confidence level indicates a smaller likelihood that the corresponding thread will actually take the predicted branch. Because speculative execution of an untaken branch wastes resources of the instruction pipeline, the processor prioritizes threads associated with a higher confidence level for selection at the stages of the instruction pipeline.

Abstract translation: 处理器使用一个或多个分支预测器来为在指令流水线上执行的每个线程发出分支预测。 基于分支预测，处理器确定每个执行线程的分支预测置信度，由此较低的置信水平表示相应线程实际上将采取预测分支的可能性较小。 由于非笔记本分支的推测执行浪费了指令流水线的资源，所以处理器将与更高置信水平相关联的线程优先排列，以在指令流水线的阶段进行选择。

公开(公告)号：US20140129772A1

公开(公告)日：2014-05-08

申请号：US13669502

申请日：2012-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Ravindra Nath Bhargava ,  Ramkumar Jayaseelan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0897

Abstract: A processor transfers prefetch requests from their targeted cache to another cache in a memory hierarchy based on a fullness of a miss address buffer (MAB) or based on confidence levels of the prefetch requests. Each cache in the memory hierarchy is assigned a number of slots at the MAB. In response to determining the fullness of the slots assigned to a cache is above a threshold when a prefetch request to the cache is received, the processor transfers the prefetch request to the next lower level cache in the memory hierarchy. In response, the data targeted by the access request is prefetched to the next lower level cache in the memory hierarchy, and is therefore available for subsequent provision to the cache. In addition, the processor can transfer a prefetch request to lower level caches based on a confidence level of a prefetch request.

Abstract translation: 处理器根据缺失地址缓冲区（MAB）的丰满度或基于预取请求的置信水平，将预取请求从目标缓存传输到存储器层次结构中的另一高速缓存。 内存层次结构中的每个高速缓存在MAB上分配了多个插槽。 响应于当接收到高速缓存的预取请求时，分配给高速缓存的时隙的丰满度高于阈值，则处理器将预取请求传送到存储器层级中的下一个较低级别的高速缓存。 作为响应，访问请求所针对的数据被预取到存储器层次结构中的下一个较低级缓存，因此可用于后续的缓存提供。 此外，处理器可以基于预取请求的置信水平将预取请求传送到较低级别的高速缓存。