公开(公告)号：US20210406180A1

公开(公告)日：2021-12-30

申请号：US17472977

申请日：2021-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan ,  Eric Christopher Morton ,  Elizabeth M. Cooper ,  Ravindra N. Bhargava

IPC: G06F12/0817 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0831

Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.

公开(公告)号：US10545875B2

公开(公告)日：2020-01-28

申请号：US15855838

申请日：2017-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Ganesh Balakrishnan ,  Ravindra N. Bhargava

IPC: G06F12/0897 ,  G06F12/121

Abstract: Systems, apparatuses, and methods for implementing a tag accelerator cache are disclosed. A system includes at least a data cache and a control unit coupled to the data cache via a memory controller. The control unit includes a tag accelerator cache (TAC) for caching tag blocks fetched from the data cache. The data cache is organized such that multiple tags are retrieved in a single access. This allows hiding the tag latency penalty for future accesses to neighboring tags and improves cache bandwidth. When a tag block is fetched from the data cache, the tag block is cached in the TAC. Memory requests received by the control unit first lookup the TAC before being forwarded to the data cache. Due to the presence of spatial locality in applications, the TAC can filter out a large percentage of tag accesses to the data cache, resulting in latency and bandwidth savings.

公开(公告)号：US20190155516A1

公开(公告)日：2019-05-23

申请号：US15818212

申请日：2017-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Philip S. Park ,  Vydhyanathan Kalyanasundharam ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

公开(公告)号：US12253961B2

公开(公告)日：2025-03-18

申请号：US16728114

申请日：2019-12-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Ravindra N. Bhargava ,  Guanhao Shen

IPC: G06F13/16 ,  G06F12/1009 ,  G11C8/12 ,  G11C11/406

Abstract: Staging memory access requests includes receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.

公开(公告)号：US20210073152A1

公开(公告)日：2021-03-11

申请号：US17100254

申请日：2020-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

公开(公告)号：US10572389B2

公开(公告)日：2020-02-25

申请号：US15839700

申请日：2017-12-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Ganesh Balakrishnan

IPC: G06F12/0895 ,  G06F12/0897

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. External system memory is used as a last-level cache and includes one of a variety of types of dynamic random access memory (DRAM). A memory controller generates a tag request and a separate data request based on a same, single received memory request. The sending of the tag request is prioritized over sending the data request. A partial tag comparison is performed during processing of the tag request. If a tag miss is detected for the partial tag comparison, then the data request is cancelled, and the memory request is sent to main memory. If one or more tag hits are detected for the partial tag comparison, then processing of the data request is dependent upon the result of the full tag comparison.

公开(公告)号：US11429281B2

公开(公告)日：2022-08-30

申请号：US16841514

申请日：2020-04-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Philip S. Park ,  Vydhyanathan Kalyanasundharam ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

公开(公告)号：US20220091991A1

公开(公告)日：2022-03-24

申请号：US17031834

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Ganesh Balakrishnan ,  Joe Sargunaraj ,  Chintan S. Patel ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0891 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0831 ,  G06F9/46

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

公开(公告)号：US20190196995A1

公开(公告)日：2019-06-27

申请号：US15850751

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/30 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1626 ,  G06F13/1642

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

公开(公告)号：US09529720B2

公开(公告)日：2016-12-27

申请号：US13912809

申请日：2013-06-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Marius Evers ,  John Kalamatianos ,  Carl D. Dietz ,  Richard E. Klass ,  Ravindra N. Bhargava

IPC: G06F12/08

CPC classification number: G06F12/0855 ,  G06F12/0844 ,  G06F12/0846

Abstract: The present application describes embodiments of techniques for picking a data array lookup request for execution in a data array pipeline a variable number of cycles behind a corresponding tag array lookup request that is concurrently executing in a tag array pipeline. Some embodiments of a method for picking the data array lookup request include picking the data array lookup request for execution in a data array pipeline of a cache concurrently with execution of a tag array lookup request in a tag array pipeline of the cache. The data array lookup request is picked for execution in response to resources of the data array pipeline becoming available after picking the tag array lookup request for execution. Some embodiments of the method may be implemented in a cache.

Abstract translation: 本申请描述了用于在数据阵列流水线中选择用于执行数据阵列查找请求的技术的实施例，该数据阵列查找请求在标签阵列管线中同时执行的对应的标签数组查找请求后面的可变数量的循环。 用于选择数据阵列查找请求的方法的一些实施例包括在高速缓存的标签阵列管线中执行标签阵列查找请求的同时，在高速缓存的数据阵列流水线中选择用于执行的数据阵列查找请求。 选择数据数组查找请求以在执行标签数组查找请求之后响应于数据数组流水线变得可用的资源进行执行。 该方法的一些实施例可以在高速缓存中实现。