公开(公告)号：US20180357865A1

公开(公告)日：2018-12-13

申请号：US16002788

申请日：2018-06-07

Applicant: Arm Limited

Inventor： Ali SAIDI

IPC: G08B7/06 ,  G06T11/60 ,  G08B17/00

CPC classification number: G08B7/066 ,  G06F3/011 ,  G06T11/60 ,  G08B5/228 ,  G08B17/00 ,  G08B21/02

Abstract: Measures, including methods, systems, processors and computer programs, for use in operating a virtual reality user device. A change in a real world environment in which a user of the virtual reality user device is physically located is detected. In response to the detection, an alert mechanism is initiated at the virtual reality user device to alert the user of the change detected in the real world environment.

公开(公告)号：US20170185528A1

公开(公告)日：2017-06-29

申请号：US15325250

申请日：2015-06-22

Applicant: ARM LIMITED

Inventor： Andreas HANSSON ,  Ali SAIDI ,  Aniruddha Nagendran UDIPI ,  Stephan DIESTELHORST

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/654 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684 ,  Y02D10/13

Abstract: A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table. The walk ahead circuitry comprises detection circuitry used to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table. In addition, the walk ahead circuitry has further request generation circuitry which is used to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request. This prefetched data may be another descriptor required as part of the address translation process, or may be the actual data item being requested by the processing circuitry. Such an approach can significantly reduce latency associated with the address translation process.

公开(公告)号：US20170371793A1

公开(公告)日：2017-12-28

申请号：US15194902

申请日：2016-06-28

Applicant: ARM Limited

Inventor： Ali SAIDI ,  Kshitij SUDAN ,  Andrew Joseph RUSHING ,  Andreas HANSSON ,  Michael FILIPPO

IPC: G06F12/0871 ,  G06F12/0873 ,  G06F12/0895

CPC classification number: G06F12/0871 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0895 ,  G06F2212/305 ,  G06F2212/401 ,  G06F2212/466

Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.

公开(公告)号：US20170024327A1

公开(公告)日：2017-01-26

申请号：US15208816

申请日：2016-07-13

Applicant: ARM Limited

Inventor： Ali SAIDI ,  Prakash S. RAMRAKHYANI

IPC: G06F12/12 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/60

Abstract: A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester.

Abstract translation: 提供了高速缓存存储器和操作高速缓冲存储器的方法。 高速缓冲存储器包括缓存存储器，其存储用于多个请求者的高速缓存行和高速缓存控制电路，当来自多个请求者之一的存储器访问请求在高速缓冲存储器中丢失时，高速缓存控制电路控制高速缓存行插入到高速缓存存储器中。 高速缓存存储器还具有高速缓存占用估计电路，该电路将所述多个请求者中的每一个的高速缓存行的高速缓存行的插入数保持在规定的时间段内。 因此，每个请求者的高速缓存行插入的计数提供了与每个请求者相关联的高速缓存占用的估计。

公开(公告)号：US20140149653A1

公开(公告)日：2014-05-29

申请号：US13684700

申请日：2012-11-26

Applicant: ARM LIMITED

Inventor： Anirruddha Nagendran UDIPI ,  Ali SAIDI ,  Andreas HANSSON ,  Christopher EMMONS

IPC: G06F12/02 ,  G11C11/406

CPC classification number: G06F12/0292 ,  G06F12/0238 ,  G06F12/06 ,  G06F12/0646 ,  G06F12/08 ,  G11C7/04 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/408

Abstract: An apparatus for processing data 2 includes a memory 4 having a plurality of memory regions 28 to 38. A mapping controller 56 applies a variable mapping to map memory addresses of access requests to different regions within the memory 4. The mapping controller varies the mapping applied in dependence upon both one or more memory behavioral parameters indicative of behavioral characteristics of the different regions and one or more access behavioral parameters indicative of behavioral characteristics of an access request to be mapped. The memory behavioral parameters may include the temperature of the regions and/or the refresh period of the regions. The access behavior able parameters may include the quality of service level, the access frequency, the access volume and/or the identity of the source of the access request.

Abstract translation: 一种用于处理数据2的装置包括具有多个存储器区域28至38的存储器4.映射控制器56应用可变映射将访问请求的存储器地址映射到存储器4内的不同区域。映射控制器改变应用的映射 依赖于指示不同区域的行为特征的一个或多个存储器行为参数以及指示要映射的访问请求的行为特征的一个或多个访问行为参数。 存储器行为参数可以包括区域的温度和/或区域的刷新周期。 访问行为能力参数可以包括服务质量水平，访问频率，访问量和/或访问请求的来源的身份。

公开(公告)号：US20140143522A1

公开(公告)日：2014-05-22

申请号：US13681801

申请日：2012-11-20

Applicant: ARM LIMITED ,  THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： Ali SAIDI ,  Thomas Friedrich WENISCH ,  Aasheesh KOLLI

IPC: G06F9/38

CPC classification number: G06F12/1027 ,  G06F9/3802 ,  G06F9/3806 ,  G06F12/0862 ,  G06F2212/6028

Abstract: An apparatus for processing data includes signature generation circuitry 30, 32 for generating a signature value indicative of the current state of the apparatus in dependence upon a sequence of immediately preceding return addresses generating during execution of a stream of program instructions to reach that state of the apparatus. Prefetch circuitry 10 performs one or more prefetch operations in dependence upon the signature value that is generated. The signature value may be generated by a hashing operation (such as an XOR) performed upon return addresses stored within a return address stack 28.

Abstract translation: 一种用于处理数据的装置包括签名生成电路30,32，用于根据在程序指令流执行期间产生的紧接在前的返回地址的序列来产生指示装置的当前状态的签名值，以达到该 仪器。 预取电路10根据生成的签名值执行一个或多个预取操作。 可以通过在返回地址堆栈28中存储的返回地址上执行的散列操作（诸如XOR）来生成签名值。