公开(公告)号：US09619937B2

公开(公告)日：2017-04-11

申请号：US14639346

申请日：2015-03-05

Applicant: ARM Limited

Inventor： Hakan Persson ,  David Shreiner

IPC: G06T17/10 ,  G06K9/62 ,  G06T1/20 ,  G06T1/60 ,  G06T7/00 ,  G06T11/40 ,  G06T15/00 ,  G06T7/50

CPC classification number: G06T17/10 ,  G06K9/6267 ,  G06T1/20 ,  G06T1/60 ,  G06T7/50 ,  G06T11/40 ,  G06T15/005

Abstract: An apparatus for processing primitives in a tile-based graphics processing system includes processing circuitry which is configured to determine, for a group of plural primitives, the rendering tiles that the group of primitives should be processed for. The processing circuitry is also configured to store, for the group of primitives, a data entry containing an indication of the identity of the plurality of primitives in the group of primitives, and an indication of the rendering tiles that it has been determined the group of primitives should be processed for.

公开(公告)号：US20150293774A1

公开(公告)日：2015-10-15

申请号：US14682302

申请日：2015-04-09

Applicant: ARM LIMITED

Inventor： Hakan Persson ,  Matt Evans ,  Jason Parker ,  Marc Zyngier

IPC: G06F9/455 ,  G06F9/44

CPC classification number: G06F9/45558 ,  G06F9/4405 ,  G06F9/4411 ,  G06F2009/45579

Abstract: A data processing system includes one or more processors that each execute one or more operating systems that include one or more applications; an accelerator that provides a shared resource for a plurality of the applications; a storage area accessible by the processors and the accelerator; and one or more input/output interfaces for control of, or the submission of tasks to, the accelerator. To initialise one of the input/output interfaces, one of the one or more processors is capable of sending a first signal to the accelerator; the accelerator is capable of writing one or more selected pieces of information representative of one or more capabilities of the accelerator to the storage area and sending a second signal to the processor; the processor is capable of reading the one or more selected pieces of information from the storage area; and the accelerator is capable of configuring the input/output interface.

Abstract translation: 数据处理系统包括一个或多个处理器，每个处理器执行包括一个或多个应用的​​一个或多个操作系统; 提供用于多个应用的​​共享资源的加速器; 由处理器和加速器可访问的存储区域; 以及一个或多个输入/输出接口，用于控制或提交加速器的任务。 为了初始化输入/输出接口之一，一个或多个处理器之一能够向加速器发送第一信号; 加速器能够将表示加速器的一个或多个能力的一个或多个选定的信息段写入存储区域，并向处理器发送第二信号; 处理器能够从存储区域读取一个或多个所选择的信息; 并且加速器能够配置输入/输出接口。

公开(公告)号：US20150089495A1

公开(公告)日：2015-03-26

申请号：US14037309

申请日：2013-09-25

Applicant: ARM Limited

Inventor： Hakan Persson ,  Wade Walker

IPC: G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/45558

Abstract: A data processing system 20 comprising an accelerator 12 that acts as a common shared resource for plural applications 3 executing in respective virtual machines 4, 5. The data processing system 20 includes an interface mapping unit 21 that facilitates the submission of tasks from applications to the accelerator 12. The interface mapping unit 21 includes physical registers 8 that act as physical register input/output interfaces for the accelerator 12. The interface mapping unit 21 exposes a plurality of virtual accelerator input/output interfaces 22 to the applications 3 that are then dynamically mapped to the physical register input/output interfaces 8 by the interface mapping unit 21 to allow applications to access, and thereby submit a task to, a given physical register input/output interface 8.

Abstract translation: 数据处理系统20包括加速器12，该加速器12用作在各个虚拟机4,5中执行的多个应用程序3的公共共享资源。数据处理系统20包括界面映射单元21，其有利于将任务从应用程序提交到 接口映射单元21包括用作​​加速器12的物理寄存器输入/输出接口的物理寄存器8.接口映射单元21将多个虚拟加速器输入/输出接口22暴露给应用3，然后动态地 通过接口映射单元21映射到物理寄存器输入/输出接口8，以允许应用程序访问，从而将任务提交给给定的物理寄存器输入/输出接口8。

公开(公告)号：US20170236244A1

公开(公告)日：2017-08-17

申请号：US15428645

申请日：2017-02-09

Applicant: ARM Limited

Inventor： Steven Price ,  Hakan Persson ,  Ian Devereux ,  Jussi Pennala

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/5066 ,  G06T1/60

Abstract: A graphics processing system comprises a pair of graphics processing units that are connected to each other via communications bridges that can allow communication between the connected graphics processing units. One of the graphics processing units is operable to act as a master graphics processing unit controlling graphics processing operations on the other graphics processing unit which is operable as a slave graphics processing unit to perform graphics processing operations under the control of the master graphics processing unit. Each graphics processing unit of the pair of graphics processing units is also capable of operating in a standalone mode, in which the graphics processing unit operates independently of the other graphics processing unit to perform a graphics processing task.

公开(公告)号：US09612949B2

公开(公告)日：2017-04-04

申请号：US13916722

申请日：2013-06-13

Applicant: ARM Limited

Inventor： Oskar Flordal ,  Hakan Persson ,  Andreas Engh-Halstvedt

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/50 ,  G06T1/60

CPC classification number: G06F12/02 ,  G06F9/5016 ,  G06F12/0284 ,  G06T1/60

Abstract: A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocator 40 needing to know the sizes of the results being produced by the processing cores.

公开(公告)号：US09454397B2

公开(公告)日：2016-09-27

申请号：US14682302

申请日：2015-04-09

Applicant: ARM Limited

Inventor： Hakan Persson ,  Matt Evans ,  Jason Parker ,  Marc Zyngier

IPC: G06F9/455 ,  G06F9/44

CPC classification number: G06F9/45558 ,  G06F9/4405 ,  G06F9/4411 ,  G06F2009/45579

Abstract: A data processing system includes one or more processors that each execute one or more operating systems that include one or more applications; an accelerator that provides a shared resource for a plurality of the applications; a storage area accessible by the processors and the accelerator; and one or more input/output interfaces for control of, or the submission of tasks to, the accelerator. To initialize one of the input/output interfaces, one of the one or more processors is capable of sending a first signal to the accelerator; the accelerator is capable of writing one or more selected pieces of information representative of one or more capabilities of the accelerator to the storage area and sending a second signal to the processor; the processor is capable of reading the one or more selected pieces of information from the storage area; and the accelerator is capable of configuring the input/output interface.

Abstract translation: 数据处理系统包括一个或多个处理器，每个处理器执行包括一个或多个应用的​​一个或多个操作系统; 提供用于多个应用的​​共享资源的加速器; 由处理器和加速器可访问的存储区域; 以及一个或多个输入/输出接口，用于控制或提交加速器的任务。 为了初始化输入/输出接口之一，一个或多个处理器之一能够向加速器发送第一信号; 加速器能够将表示加速器的一个或多个能力的一个或多个选定的信息段写入存储区域，并向处理器发送第二信号; 处理器能够从存储区域读取一个或多个所选择的信息; 并且加速器能够配置输入/输出接口。

公开(公告)号：US10467140B2

公开(公告)日：2019-11-05

申请号：US15099119

申请日：2016-04-14

Applicant: ARM Limited

Inventor： Roko Grubisic ,  Hakan Persson ,  Neil Andrew Jameson

IPC: G06F12/0831 ,  G06F9/46 ,  G06F12/128 ,  G06F12/1027

Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.

公开(公告)号：US10261813B2

公开(公告)日：2019-04-16

申请号：US14037309

申请日：2013-09-25

Applicant: ARM Limited

Inventor： Hakan Persson ,  Wade Walker

IPC: G06F9/455

Abstract: A data processing system comprising an accelerator that acts as a common shared resource for plural applications executing in respective virtual machines. The data processing system includes an interface mapping unit that facilitates the submission of tasks from applications to the accelerator. The interface mapping unit includes physical registers that act as physical register input/output interfaces for the accelerator. The interface mapping unit exposes a plurality of virtual accelerator input/output interfaces to the applications that are then dynamically mapped to the physical register input/output interfaces by the interface mapping unit to allow applications to access, and thereby submit a task to, a given physical register input/output interface.

公开(公告)号：US09672162B2

公开(公告)日：2017-06-06

申请号：US13969277

申请日：2013-08-16

Applicant: ARM Limited

Inventor： Hakan Persson ,  Sean Tristram Ellis

IPC: G06F12/14

CPC classification number: G06F12/1458 ,  G06F12/1433

Abstract: A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regions 9 but no or write-only access to any protected memory regions 8, and a protected mode of operation in which it has read and write access to data that is stored in protected memory regions 8 but only has read-only access to any non-protected memory regions 9. The data processing system further comprises a mechanism for switching the graphics processing unit from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

公开(公告)号：US20150293775A1

公开(公告)日：2015-10-15

申请号：US14682310

申请日：2015-04-09

Applicant: ARM Limited

Inventor： Hakan Persson ,  Matt Evans ,  Jason Parker ,  Marc Zyngier

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A data processing system comprises one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. The system also comprises an accelerator that provides a shared resource for a plurality of the applications, an input/output module comprising one or more input/output interfaces for the submission of tasks to the accelerator, a hypervisor that manages the allocation of the input/output interfaces to the one or more operating systems and a storage area accessible by the hypervisor and the accelerator. The accelerator is capable of writing one or more selected pieces of information representative of one or more scheduling statistics of the accelerator periodically to the storage area without having received a request for the one or more selected pieces of information from the hypervisor.

Abstract translation: 数据处理系统包括一个或多个处理器，每个处理器执行一个或多个操作系统。 每个操作系统包括一个或多个应用程序。 该系统还包括为多个应用提供共享资源的加速器，包括用于向加速器提交任务的一个或多个输入/输出接口的输入/输出模块，管理程序，用于管理输入/ 输出到一个或多个操作系统的接口以及由管理程序和加速器可访问的存储区域。 加速器能够将表示加速器的一个或多个调度统计信息的一个或多个选定的信息段周期性地写入存储区域，而不从管理程序接收到对于一个或多个所选择的信息的请求。