公开(公告)号：US09786362B1

公开(公告)日：2017-10-10

申请号：US15248335

申请日：2016-08-26

Applicant: ARM Limited

Inventor： Shidhartha Das ,  David Michael Bull ,  Pranay Prabhat ,  Adeline-Fleur Fleming

IPC: G11C8/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C2207/2236

Abstract: A memory circuit comprises an array of data storage elements; access circuitry to access a data bit, stored by a data storage element enabled for access, by an access signal for that data storage element; and control circuitry to enable groups of data storage elements for access, the groups having a group size, the group size being one or more, the access signals for data storage elements in a group being combined to provide a combined access signal common to that group of data storage elements; the control circuitry being configured to selectively operate in at least a first mode and a second mode, the group size in the first mode being different to the group size in the second mode.

公开(公告)号：US10997322B2

公开(公告)日：2021-05-04

申请号：US15967900

申请日：2018-05-01

Applicant: Arm Limited

Inventor： Adeline-Fleur Fleming ,  Carl Wayne Vineyard ,  George Mcneil Lattimore ,  Christopher Neal Hinds ,  Robert John Harrison ,  Mikael Rien ,  Abdellah Bakhali ,  Robert Christiaan Schouten ,  Jean-Charles Bolinhas

IPC: G06F21/75 ,  H02J7/00 ,  H03K5/24 ,  H01L27/00 ,  H02J7/34 ,  H03K17/687 ,  H03K3/03

Abstract: An apparatus is provided to enable power supply input to be isolated from power supply output. Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply. The first charge store can be charged from the power input whilst isolated from the power output. The second charge store can be discharged to the power output, while isolated from the power input.

公开(公告)号：US11361111B2

公开(公告)日：2022-06-14

申请号：US16030459

申请日：2018-07-09

Applicant: Arm Limited

Inventor： Carl Wayne Vineyard ,  Christopher Neal Hinds ,  Adeline-Fleur Fleming

IPC: G06F21/77 ,  G06F21/56 ,  G06F21/72

Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.

公开(公告)号：US10924261B2

公开(公告)日：2021-02-16

申请号：US15600974

申请日：2017-05-22

Applicant: ARM Limited

Inventor： Robert John Harrison ,  Mikael Rien ,  Carl Wayne Vineyard ,  George Mcneil Lattimore ,  Christopher Neal Hinds ,  Adeline-Fleur Fleming

IPC: H04L9/00 ,  G06F1/26

Abstract: An apparatus includes a power input, a power output, and a plurality of independent powering units each comprising at least one charge store. Each of the plurality of powering units is capable of receiving power from the power input while isolating the power output, and each of the plurality of powering units is capable of outputting power to the power output while isolating the power input.