公开(公告)号：US10924261B2

公开(公告)日：2021-02-16

申请号：US15600974

申请日：2017-05-22

申请人： ARM Limited

发明人： Robert John Harrison ,  Mikael Rien ,  Carl Wayne Vineyard ,  George Mcneil Lattimore ,  Christopher Neal Hinds ,  Adeline-Fleur Fleming

IPC分类号： H04L9/00 ,  G06F1/26

摘要： An apparatus includes a power input, a power output, and a plurality of independent powering units each comprising at least one charge store. Each of the plurality of powering units is capable of receiving power from the power input while isolating the power output, and each of the plurality of powering units is capable of outputting power to the power output while isolating the power input.

公开(公告)号：US09831876B2

公开(公告)日：2017-11-28

申请号：US14814029

申请日：2015-07-30

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components.

公开(公告)号：US20150346803A1

公开(公告)日：2015-12-03

申请号：US14728987

申请日：2015-06-02

申请人： ARM Limited

发明人： Jean-Claude Duby ,  Mikael Rien

IPC分类号： G06F1/32

CPC分类号： G06F1/3243 ,  G06F1/189 ,  G06F1/26 ,  G06F3/047 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K9/0039 ,  H05K2201/10522 ,  H05K2201/10734

摘要： An integrated circuit is provided with interface circuitry used to provide an interface between functional circuitry of the integrated circuit and components external to the integrated circuit. The interface circuitry includes a plurality of interface cells having interface components configured to operate from a first power supply. Each interface cell incorporates a power supply line section extending across its width and configured to cooperate with power supply line sections of other interface cells to provide a power supply line structure shared by the plurality of interface cells, for provision of the first power supply to the interface components. Each power supply line section includes a first supply line portion and a second supply line portion, the first supply line portion being sized to support a current carrying constraint of the interface circuitry, whilst the second supply line portion is sized insufficiently to support that current carrying constraint. Instead, each interface cell is arranged within the interface circuitry such that the second supply line portion is connected to a current carrying structure external to that interface cell, such that the second supply line portion in combination with the connected current carrying structure is sized sufficiently to support the current carrying constraint. Such an approach enables a reduction in the area required for the power supply line structure, hence enabling a reduction in the size of the interface circuitry, and accordingly a corresponding reduction in the required size of the integrated circuit.

摘要翻译： 集成电路设置有用于提供集成电路的功能电路与集成电路外部的组件之间的接口的接口电路。 接口电路包括具有被配置为从第一电源操作的接口部件的多个接口单元。 每个接口单元包括延伸跨越其宽度的电源线部分，并且被配置为与其他接口单元的电源线部分配合，以提供由多个接口单元共享的电源线结构，以将第一电源提供给 接口组件。 每个电源线部分包括第一供应线部分和第二供应线部分，第一供应线部分的尺寸被设计成支持接口电路的电流承载约束，而第二供应线部分的尺寸不足以支持该载流 约束。 相反，每个接口单元被布置在接口电路内，使得第二供电线部分连接到该接口单元外部的载流结构，使得第二供电线部分与连接的载流结构相结合， 支持当前的携带约束。 这种方法使得能够减少供电线路结构所需的面积，从而能够减小接口电路的尺寸，并且相应地减小集成电路所需的尺寸。

公开(公告)号：US10340917B2

公开(公告)日：2019-07-02

申请号：US15823481

申请日：2017-11-27

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K19/185 ,  H03K19/0185

摘要： The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components.

公开(公告)号：US09831855B1

公开(公告)日：2017-11-28

申请号：US15155003

申请日：2016-05-14

申请人： ARM Limited

发明人： Seshagiri Rao Bogi ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K5/06 ,  H03K3/3565 ,  H03K19/00

CPC分类号： H03K5/06 ,  H03K3/3565 ,  H03K19/0013 ,  H03K19/018521

摘要： Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

公开(公告)号：US20170331465A1

公开(公告)日：2017-11-16

申请号：US15155003

申请日：2016-05-14

申请人： ARM Limited

发明人： Seshagiri Rao Bogi ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K5/06 ,  H03K19/00 ,  H03K3/3565

CPC分类号： H03K5/06 ,  H03K3/3565 ,  H03K19/0013 ,  H03K19/018521

摘要： Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

公开(公告)号：US20170041002A1

公开(公告)日：2017-02-09

申请号：US15331536

申请日：2016-10-21

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien ,  Vikas Murli Kyatsandra

IPC分类号： H03K19/0175 ,  H03K19/0948 ,  H03K19/003

CPC分类号： H03K19/017509 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/0948

摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal. The integrated circuit may include signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals. The integrated circuit may include signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal. The integrated circuit may include signal protection circuitry that receives the input signal from the first voltage domain, receives the intermediate signal from the signal evaluation circuitry, and allows the input signal until the intermediate signal transitions between a first state and a second state that is different than the first state.

摘要翻译： 本文描述的各种实施方式涉及集成电路。 集成电路可以包括从第一电压域接收输入信号并基于输入信号产生多个内部信号的信号发生电路。 集成电路可以包括从信号产生电路接收多个内部信号并且基于多个内部信号提供中间信号的信号评估电路。 集成电路可以包括信号转换电路，其接收中间信号并且基于中间信号为第二电压域提供输出信号。 集成电路可以包括信号保护电路，其接收来自第一电压域的输入信号，从信号评估电路接收中间信号，并允许输入信号，直到中间信号在不同的第一状态和第二状态之间转换 比第一个状态。

公开(公告)号：US20160036445A1

公开(公告)日：2016-02-04

申请号：US14814029

申请日：2015-07-30

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components.

摘要翻译： 本发明提供了一种用于从源极电压域接收输入信号并将输入信号转换为目的地电压域的输出信号的接收机电路和方法。 源极电压域从超过接收器电路内的部件的应力阈值的电源电压操作，并且接收器电路被配置为从源极电压域的电源电压进行工作。 接收器电路包括配置成将输入信号转换成第一电压范围内的第一内部信号的第一内部信号产生电路，以及被配置为在第二电压范围内将输入信号转换为第二内部信号的第二内部信号产生电路。 信号评估电路根据电源电压建立逻辑高电压阈值和逻辑低电压阈值，并采用第一和第二内部信号，以便在输入信号转换时基于逻辑高电压阈值和逻辑低电压阈值进行检测 在逻辑低电平和逻辑高电平之间（在任一方向上）。 然后，输出产生电路根据由信号评估电路执行的检测产生输出信号。 第一电压范围和第二电压范围使得第一内部信号和第二内部信号不会超过信号评估电路中的组件的应力阈值。 在源极电压域的电源电压超过接收器部件的应力阈值但没有接收器部件的过应力的情况下，接收器电路能够可靠地检测输入信号中的转变。

公开(公告)号：US09933835B2

公开(公告)日：2018-04-03

申请号：US14728987

申请日：2015-06-02

申请人： ARM Limited

发明人： Jean-Claude Duby ,  Mikael Rien

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F3/047 ,  G06F1/18 ,  H01L23/50 ,  H05K9/00

CPC分类号： G06F1/3243 ,  G06F1/189 ,  G06F1/26 ,  G06F3/047 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K9/0039 ,  H05K2201/10522 ,  H05K2201/10734

摘要： An integrated circuit is provided with interface circuitry used to provide an interface between functional circuitry of the integrated circuit and components external to the integrated circuit. The interface circuitry includes a plurality of interface cells having interface components configured to operate from a first power supply. Each interface cell incorporates a power supply line section extending across its width and configured to cooperate with power supply line sections of other interface cells to provide a power supply line structure shared by the plurality of interface cells, for provision of the first power supply to the interface components. Each power supply line section includes a first supply line portion and a second supply line portion, the first supply line portion being sized to support a current carrying constraint of the interface circuitry, while the second supply line portion is sized insufficiently to support that current carrying constraint. Instead, each interface cell is arranged within the interface circuitry such that the second supply line portion is connected to a current carrying structure external to that interface cell, such that the second supply line portion in combination with the connected current carrying structure is sized sufficiently to support the current carrying constraint. Such an approach enables a reduction in the area required for the power supply line structure, hence enabling a reduction in the size of the interface circuitry, and accordingly a corresponding reduction in the required size of the integrated circuit.

公开(公告)号：US09806716B2

公开(公告)日：2017-10-31

申请号：US14814180

申请日：2015-07-30

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0185 ,  H03K3/356

CPC分类号： H03K19/00315 ,  H03K3/35613 ,  H03K3/356165 ,  H03K3/356182 ,  H03K19/0013 ,  H03K19/00384 ,  H03K19/018521

摘要： Output signal generation circuitry 100 may be used for converting an input signal 110 from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry 160 operating from the supply voltage, which is configured to generate at an output node 130 the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry 280A, 280B, 280C, 280D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal. Timing compensation circuitry 180A, 180B may also be provided, to control the voltage on the output node in a manner to compensate for the delay introduced by the tracking circuitry.