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    TECHNIQUE FOR MANAGING POWER DOMAINS IN AN INTEGRATED CIRCUIT
    1.
    发明申请
    TECHNIQUE FOR MANAGING POWER DOMAINS IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190187770A1

    公开(公告)日：2019-06-20

    申请号：US16190377

    申请日：2018-11-14

    Applicant: Arm Limited

    Inventor： Christopher Vincent SEVERINO ,  Dominic William BROWN ,  Ashley John CRAWFORD

    IPC: G06F1/32

    CPC classification number: G06F1/3234

    Abstract: An integrated circuit and method are provided for managing power domains. The integrated circuit has first circuitry provided within a first power domain, and a distributed power controller for controlling transition of the first power domain between a plurality of power states. The distributed power controller comprises at least power control circuitry in a second power domain and additional power control circuitry in a third power domain. Whilst the current power state of the first power domain is in any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain. However, the third power domain is prevented from entering that power saving state. Further, the additional power control circuitry is arranged to output a mode status signal that is then used by the power control circuitry, when the second power domain exits the power saving state, to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain. This ensures that, despite the power control circuitry losing knowledge of the current power state of the first power domain whilst it is in the power saving state, no unintended consequences occur when the second power domain subsequently exits the power saving state.

    GATHERING MONITORING DATA RELATING TO THE OPERATION OF A DATA PROCESSING SYSTEM
    4.
    发明申请
    GATHERING MONITORING DATA RELATING TO THE OPERATION OF A DATA PROCESSING SYSTEM 审中-公开
    与数据处理系统的操作相关的监控数据

    公开(公告)号：US20170026255A1

    公开(公告)日：2017-01-26

    申请号：US15191950

    申请日：2016-06-24

    Applicant: ARM LIMITED

    Inventor： John Michael HORLEY ,  Christopher Vincent SEVERINO

    IPC: H04L12/26

    CPC classification number: H04L43/04 ,  H04L43/12

    Abstract: A system, apparatus and method for gathering monitoring data relating to the operation of a data processing system are disclosed. The data processing system comprises a monitor controller and a plurality of monitors which gather monitoring data relating to the operation of the data processing system. Each monitor does not send its monitoring data to the monitor controller unsolicited, but merely indicates to the monitor controller that it has such data ready for transmission. In response to reception of a data ready signal from more than one monitor, the monitor controller selects one of these monitors and sends it a data transmission command, thereby avoiding resource contention in a shared resource between data transmissions from more than one monitor.

    Abstract translation: 公开了一种用于收集与数据处理系统的操作相关的监控数据的系统，装置和方法。 数据处理系统包括监视器控制器和收集与数据处理系统的操作有关的监视数据的多个监视器。 每个监视器不会将其监视数据发送到监视器控制器，而是仅向监视器控制器指示其具有准备传输的数据。 响应于来自多个监视器的数据就绪信号的接收，监视器控制器选择这些监视器中的一个并向其发送数据传输命令，从而避免来自多于一个监视器的数据传输之间的共享资源中的资源争用。

    BUILT-IN SELF-TEST IN A DATA PROCESSING APPARATUS
    5.
    发明申请
    BUILT-IN SELF-TEST IN A DATA PROCESSING APPARATUS 审中-公开

    公开(公告)号：US20200278395A1

    公开(公告)日：2020-09-03

    申请号：US16289741

    申请日：2019-03-01

    Applicant: Arm Limited

    Inventor： Joseph Samuel HERD ,  Kar-Lik Kasim WONG ,  Christopher Vincent SEVERINO

    IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G06F9/4401

    Abstract: Apparatuses and methods of controlling an apparatus are disclosed. An apparatus comprises a control domain comprising functional circuitry to perform logical operations when in an operational state, wherein the functional circuitry comprises at least one output and a state of the at least one output is dependent on the logical operations. Domain control circuitry controls the control domain to put the functional circuitry in one of the operational state and a non-operational state. Isolation circuitry isolates the functional circuitry within the apparatus by holding the state of the at least one output at a predetermined value when the domain control circuitry puts the functional circuitry in the non-operational state. Self-test control circuitry causes the domain control circuitry to control the control domain to put the functional circuitry in the non-operational state and to cause a self-test procedure to be carried out with respect to the functional circuitry.

    ADDRESS SPACE ACCESS CONTROL
    6.
    发明申请
    ADDRESS SPACE ACCESS CONTROL 审中-公开

    公开(公告)号：US20190146693A1

    公开(公告)日：2019-05-16

    申请号：US16170371

    申请日：2018-10-25

    Applicant: Arm Limited

    Inventor： Christopher Vincent SEVERINO ,  Seow Chuan LIM ,  Aris Doros ARISTODEMOU ,  Matthew Lucien EVANS

    IPC: G06F3/06 ,  G06F12/14

    Abstract: There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.

    INTERFACE APPARATUS AND METHOD
    7.
    发明申请
    INTERFACE APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20180004704A1

    公开(公告)日：2018-01-04

    申请号：US15603769

    申请日：2017-05-24

    Applicant: ARM Limited

    Inventor： Peter CZAKÓ ,  Seow Chuan LIM ,  Dominic William BROWN ,  Christopher Vincent SEVERINO ,  Patrick Michael OVERS

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/28 ,  G06F13/364

    CPC classification number: G06F13/4295 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/364

    Abstract: An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is currently ready to receive the data item.

    DATA COMMUNICATION APPARATUS AND METHOD
    8.
    发明申请
    DATA COMMUNICATION APPARATUS AND METHOD 有权

    公开(公告)号：US20230019132A1

    公开(公告)日：2023-01-19

    申请号：US17811757

    申请日：2022-07-11

    Applicant: Arm Limited

    Inventor： Christopher Vincent SEVERINO

    IPC: H04L47/34 ,  H04L47/43

    Abstract: A data communication apparatus having a message receiver, and a message transmitter to transmit messages to the message receiver. The message transmitter being configured to partition a payload greater than a predetermined size into a set of plural successive messages each being no larger than the predetermined size and to associate one or more flags with respective ones of the set of plural successive messages, the one or more flags indicating an ordering of messages within a set of plural successive messages, and the message receiver having a buffer to buffer received messages of a set of plural successive messages to reassemble a payload represented by the given set of plural successive messages, and a detector to detect an expected ordering of the one or more flags with respect to receipt by the message receiver of messages of a given set of plural successive messages.

    METHODS AND APPARATUS FOR INTERFACING BETWEEN POWER DOMAINS
    9.
    发明申请
    METHODS AND APPARATUS FOR INTERFACING BETWEEN POWER DOMAINS 有权

    公开(公告)号：US20210026439A1

    公开(公告)日：2021-01-28

    申请号：US16521671

    申请日：2019-07-25

    Applicant: Arm Limited

    Inventor： Dominic William BROWN ,  Christopher Vincent SEVERINO

    IPC: G06F1/3296 ,  G06F1/3206

    Abstract: Aspects of the present disclosure relate to power bridge circuitry comprising a first interface configured to interface with a source power domain; a second interface configured to interface with a target power domain; transition circuitry to receive a transition indication that the power bridge circuitry is to transition to an idle state; communication circuitry to communicate messages between the interfaces; and message identification circuitry to identify messages communicated by the communication circuitry, the identification circuitry being configured to detect the communication of a given message directed to a target component connected to the second interface and indicating cessation of communication between the target component and a source component connected to the first interface. The transition circuitry is configured, responsive to receiving the transition indication and responsive to the message identification circuitry detecting communication of the given message, to initiate a transition of the power bridge circuitry to the idle state.

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