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公开(公告)号：US20240302986A1
公开(公告)日：2024-09-12
申请号：US18664586
申请日：2024-05-15
Applicant: Arm Limited
Inventor： Seow Chuan LIM , Steven Douglas KRUEGER
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0604 , G06F3/0631 , G06F3/0659 , G06F3/0673
Abstract: An apparatus includes processing circuitry that performs data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier, and configuration application circuitry applies the set of memory transaction parameters with respect to memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation and a maximum target allocation of a storage capacity of at least part of a memory system in handling the memory transaction that identifies the partition identifier.
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公开(公告)号：US20180225168A1
公开(公告)日：2018-08-09
申请号：US15428550
申请日：2017-02-09
Applicant: ARM Limited
Inventor： Anitha KONA , Michael Wayne GARNER , Randall L. JONES , Tessil THOMAS , Seow Chuan LIM , Karthick SANTHANAM , Liana Christine Nicklaus
CPC classification number: G06F11/0757 , G06F13/24
Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.
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公开(公告)号：US20190146693A1
公开(公告)日：2019-05-16
申请号：US16170371
申请日：2018-10-25
Applicant: Arm Limited
Inventor： Christopher Vincent SEVERINO , Seow Chuan LIM , Aris Doros ARISTODEMOU , Matthew Lucien EVANS
Abstract: There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.
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公开(公告)号：US20180004704A1
公开(公告)日：2018-01-04
申请号：US15603769
申请日：2017-05-24
Applicant: ARM Limited
Inventor： Peter CZAKÓ , Seow Chuan LIM , Dominic William BROWN , Christopher Vincent SEVERINO , Patrick Michael OVERS
IPC: G06F13/42 , G06F13/16 , G06F13/28 , G06F13/364
CPC classification number: G06F13/4295 , G06F13/1673 , G06F13/28 , G06F13/364
Abstract: An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is currently ready to receive the data item.
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Patent Agency Ranking
公开(公告)号：US20230064619A1
公开(公告)日：2023-03-02
申请号：US17822473
申请日：2022-08-26
Applicant: Arm Limited
Inventor： Seow Chuan LIM , Zhuoran WANG , Gergely TÓTH , Péter CZAKÓ , Barnabás SIPOS , Dezso Imre NOVAK
Abstract: A direct memory access (DMA) controller comprises template storage circuitry to store at least one DMA template indicative of a DMA data access pattern. Each DMA template comprises enable indications settable to an enable state or a disable state. In response to a DMA command associated with a source address, a destination address, a source DMA template, and a destination DMA template, DMA control circuitry generates a set of DMA memory access requests to copy data from source memory system locations to destination memory system locations. The source/destination memory system locations are selected to have addresses which are offset relative to the source/destination address by offset amounts corresponding to positions of enable indications set to the enable state within the source/destination DMA template. The source/destination DMA templates allow irregular patterns of DMA accesses to be controlled in fewer DMA commands.
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公开(公告)号：US20190073011A1
公开(公告)日：2019-03-07
申请号：US16035884
申请日：2018-07-16
Applicant: ARM Limited
Inventor： Richard Andrew PATERSON , Seow Chuan LIM , Alessandro RENZI
Abstract: An integrated circuit comprises first and second power domains, and a message handling unit to control passing of messages sent from a sender device in the first power domain to a receiver device in the second power domain. The message handling unit writes messages sent from the sender device to a message storage area, provided in the second power domain. The message handling unit is responsive to a message send request from the sender device requesting sending of at least one message to the receiver device when at least one device in the second power domain is in a quiescent state, to transmit a wakeup request to a second domain power controller to request that said at least one device in the second power domain transitions from the quiescent state to an awake state.
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公开(公告)号：US20220382475A1
公开(公告)日：2022-12-01
申请号：US17330724
申请日：2021-05-26
Applicant: Arm Limited
Inventor： Seow Chuan LIM , Steven Douglas KRUEGER
IPC: G06F3/06
Abstract: An apparatus includes processing circuitry configured that performs data processing in response to instructions of one of a plurality of software execution environments. First stage partition identifier remapping circuitry remaps a partition identifier specified for a memory transaction by a first software execution environment to a internal partition identifier to be specified with the memory transaction issued to at least one memory system component. In response to a memory transaction to be handled, the at least one memory system component controls allocation of resources for handling the memory transaction or manage contention for the resources in dependence on a selected set of memory system component parameters selected in dependence on the internal partition identifier specified by the memory transaction. Second stage partition identifier remapping circuitry dynamically overrides the internal partition identifier to be specified with the memory transaction based on a sideband input signal and the first stage partition identifier remapping circuitry indicates, for the partition identifier, whether the second stage partition identifier remapping circuitry is to be used.
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公开(公告)号：US20220382474A1
公开(公告)日：2022-12-01
申请号：US17330722
申请日：2021-05-26
Applicant: Arm Limited
Inventor： Seow Chuan LIM , Steven Douglas KRUEGER
IPC: G06F3/06
Abstract: An apparatus includes processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier and configuration application circuitry applies the set of memory transaction parameters in respect of memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation of a resource used by a memory system in handling the memory transaction that identifies the partition identifier. Also provided is an apparatus that comprises processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters and associated partition identifiers. The memory transaction parameters comprise resource allocations for handling transactions that identify the associated partition identifier. Configuration application circuitry performs the resource allocations. The memory transaction parameters comprise an enable setting and the configuration application circuitry inhibits the resource allocations based on the enable setting.
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公开(公告)号：US20180004278A1
公开(公告)日：2018-01-04
申请号：US15593729
申请日：2017-05-12
Applicant: ARM Limited
Inventor： Seow Chuan LIM , Dominic William BROWN , Christopher Vincent SEVERINO , Gergely KISS , Csaba Kelemen
CPC classification number: G06F1/3287 , G06F1/3246 , G06F9/4418 , G11C5/14 , H03K19/00 , H03K19/0016 , Y02D10/171
Abstract: A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable.
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