公开(公告)号：US20180254084A1

公开(公告)日：2018-09-06

申请号：US15966230

申请日：2018-04-30

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Lucian Shifren ,  Piyush Agarwal ,  Akshay Kumar ,  Robert Campbell Aitken

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/79 ,  G11C2213/82

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.

公开(公告)号：US20180247693A1

公开(公告)日：2018-08-30

申请号：US15936212

申请日：2018-03-26

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Vivek Asthana ,  Piyush Agarwal ,  Akshay Kumar ,  Lucian Shifren

IPC分类号： G11C13/00 ,  H01L27/24

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/79 ,  G11C2213/82

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.

公开(公告)号：US09972388B2

公开(公告)日：2018-05-15

申请号：US15291627

申请日：2016-10-12

申请人： ARM Ltd.

发明人： Shidhartha Das ,  Piyush Agarwal ,  Akshay Kumar ,  Azeez Jennudin Bhavnagarwala

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0097 ,  G11C16/20

摘要： Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.

公开(公告)号：US20180114574A1

公开(公告)日：2018-04-26

申请号：US15334187

申请日：2016-10-25

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Lucian Shifren ,  Piyush Agarwal ,  Akshay Kumar ,  Robert Campbell Aitken

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/79 ,  G11C2213/82

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.

公开(公告)号：US10431304B2

公开(公告)日：2019-10-01

申请号：US15936212

申请日：2018-03-26

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Vivek Asthana ,  Piyush Agarwal ,  Akshay Kumar ,  Lucian Shifren

IPC分类号： G11C13/00

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.

公开(公告)号：US10381076B2

公开(公告)日：2019-08-13

申请号：US15865116

申请日：2018-01-08

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Vikas Chandra ,  Brian Tracy Cline

IPC分类号： H03M1/00 ,  G11C13/00 ,  G11C11/38 ,  G11C17/12 ,  H03M1/78 ,  H03M1/80

摘要： A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

公开(公告)号：US10127981B2

公开(公告)日：2018-11-13

申请号：US15966230

申请日：2018-04-30

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Lucian Shifren ,  Piyush Agarwal ,  Akshay Kumar ,  Robert Campbell Aitken

IPC分类号： G11C11/00 ,  G11C13/00

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.

公开(公告)号：US09990992B2

公开(公告)日：2018-06-05

申请号：US15334187

申请日：2016-10-25

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Lucian Shifren ,  Piyush Agarwal ,  Akshay Kumar ,  Robert Campbell Aitken

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/79 ,  G11C2213/82

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.

公开(公告)号：US10062435B2

公开(公告)日：2018-08-28

申请号：US15711998

申请日：2017-09-21

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Piyush Agarwal ,  Akshay Kumar

IPC分类号： G11C13/00 ,  G11C11/16

CPC分类号： G11C13/004 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C13/0097

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.

公开(公告)号：US09947402B1

公开(公告)日：2018-04-17

申请号：US15443960

申请日：2017-02-27

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Vivek Asthana ,  Piyush Agarwal ,  Akshay Kumar ,  Lucian Shifren

IPC分类号： G11C13/00 ,  H01L27/24

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436

摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.