公开(公告)号：US20210407789A1

公开(公告)日：2021-12-30

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20230230833A1

公开(公告)日：2023-07-20

申请号：US18127201

申请日：2023-03-28

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H10B43/27

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H10B43/27

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20210057275A1

公开(公告)日：2021-02-25

申请号：US16995281

申请日：2020-08-17

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538

Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.

公开(公告)号：US12040229B2

公开(公告)日：2024-07-16

申请号：US17989875

申请日：2022-11-18

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed

IPC: H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76879 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76802 ,  H01L23/5384 ,  H10B41/27 ,  H10B43/27

Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.

公开(公告)号：US11594450B2

公开(公告)日：2023-02-28

申请号：US16995281

申请日：2020-08-17

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538 ,  G11C5/02

Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.

公开(公告)号：US11501968B2

公开(公告)日：2022-11-15

申请号：US17093224

申请日：2020-11-09

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Anna Trovato ,  Kelly Houben ,  Steven van Aerde ,  Bert Jongbloed ,  Wilco A. Verweij

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/331 ,  H01L27/092 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/285

Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.

公开(公告)号：US11646204B2

公开(公告)日：2023-05-09

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20230084173A1

公开(公告)日：2023-03-16

申请号：US17989875

申请日：2022-11-18

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538 ,  G11C5/02

Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.

公开(公告)号：US20210151315A1

公开(公告)日：2021-05-20

申请号：US17093224

申请日：2020-11-09

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Anna Trovato ,  Kelly Houben ,  Steven van Aerde ,  Bert Jongbloed ,  Wilco A. Verweij

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/285

Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.