公开(公告)号：US20230223258A1

公开(公告)日：2023-07-13

申请号：US18153282

申请日：2023-01-11

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Kelly Houben ,  Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Charles Dezelah

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  C30B25/18

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L21/02661 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  C30B25/186

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer

公开(公告)号：US20210407789A1

公开(公告)日：2021-12-30

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20230220588A1

公开(公告)日：2023-07-13

申请号：US18153254

申请日：2023-01-11

Applicant: ASM IP Holding B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Dieter Pierreux ,  Kelly Houben ,  Bert Jongbloed ,  Peter Westrom

IPC: C30B29/68 ,  H01L21/677 ,  H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52

CPC classification number: C30B29/68 ,  H01L21/67742 ,  H01L21/02532 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/0262 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02433

Abstract: A method of forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a semiconductor processing apparatus. This semiconductor processing apparatus comprises a process chamber and a carousel for stationing a wafer boat before or after processing in the process chamber. The method further comprises loading the wafer boat into the process chamber, the wafer boat comprising the plurality of substrates. The method further comprises processing the plurality of substrates in the process chamber, thereby forming, on the plurality of substrates, the epitaxial stack. This epitaxial stack has a pre-determined thickness. The processing comprises unloading the wafer boat, one or more times, from the process chamber to the carousel until the epitaxial stack reaches the pre-determined thickness.

公开(公告)号：US20230230833A1

公开(公告)日：2023-07-20

申请号：US18127201

申请日：2023-03-28

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H10B43/27

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H10B43/27

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20230223255A1

公开(公告)日：2023-07-13

申请号：US18153272

申请日：2023-01-11

Applicant: ASM IP Holding, B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Dieter Pierreux ,  Kelly Houben ,  Rami Khazaka ,  Frederick Aryeetey ,  Peter Westrom ,  Omar Elleuch ,  Caleb Miskin

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68

CPC classification number: H01L21/0257 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/0262 ,  H01L21/02532

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

公开(公告)号：US11646204B2

公开(公告)日：2023-05-09

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.