公开(公告)号：US20210407789A1

公开(公告)日：2021-12-30

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20230220588A1

公开(公告)日：2023-07-13

申请号：US18153254

申请日：2023-01-11

Applicant: ASM IP Holding B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Dieter Pierreux ,  Kelly Houben ,  Bert Jongbloed ,  Peter Westrom

IPC: C30B29/68 ,  H01L21/677 ,  H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52

CPC classification number: C30B29/68 ,  H01L21/67742 ,  H01L21/02532 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/0262 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02433

Abstract: A method of forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a semiconductor processing apparatus. This semiconductor processing apparatus comprises a process chamber and a carousel for stationing a wafer boat before or after processing in the process chamber. The method further comprises loading the wafer boat into the process chamber, the wafer boat comprising the plurality of substrates. The method further comprises processing the plurality of substrates in the process chamber, thereby forming, on the plurality of substrates, the epitaxial stack. This epitaxial stack has a pre-determined thickness. The processing comprises unloading the wafer boat, one or more times, from the process chamber to the carousel until the epitaxial stack reaches the pre-determined thickness.

公开(公告)号：US20230223258A1

公开(公告)日：2023-07-13

申请号：US18153282

申请日：2023-01-11

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Kelly Houben ,  Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Charles Dezelah

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  C30B25/18

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L21/02661 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  C30B25/186

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer

公开(公告)号：US11501968B2

公开(公告)日：2022-11-15

申请号：US17093224

申请日：2020-11-09

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Anna Trovato ,  Kelly Houben ,  Steven van Aerde ,  Bert Jongbloed ,  Wilco A. Verweij

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/331 ,  H01L27/092 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/285

Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.

公开(公告)号：US20250079159A1

公开(公告)日：2025-03-06

申请号：US18815701

申请日：2024-08-26

Applicant: ASM IP Holding, B.V.

Inventor： Dieter Pierreux ,  Steven Van Aerde ,  Kelly Houben ,  Bert Jongbloed

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455

Abstract: The technology of the present disclosure generally relates to the field of semiconductor devices. More particularly, semiconductor structures, systems, and methods for producing the same, comprising surface-modified silicon layers formed by reacting a deposited silicon layer with a halide reactant. The system comprising one or more reaction chamber constructed and arranged to hold a substrate; a silicon precursor vessel constructed and arranged to contain and evaporate a silicon precursor; a halide reactant vessel constructed and arranged to contain and evaporate a halide reactant; an exhaust source; and a controller; wherein the controller is configured to control the flow of said silicon precursor and said halide reactant into said reaction chamber, thereby forming a surface-modified silicon layer on said substrate.

公开(公告)号：US20240420971A1

公开(公告)日：2024-12-19

申请号：US18741168

申请日：2024-06-12

Applicant: ASM IP Holding B.V.

Inventor： Subir Parui ,  Kelly Houben ,  Theodorus Oosterlaken ,  Herbert Terhorst ,  Bert Jongbloed

IPC: H01L21/67 ,  H01L21/687

Abstract: A vertical furnace and a method for processing a plurality of substrates in said vertical furnace is disclosed. Embodiments of the presently described vertical furnace comprise a process chamber, a heating element configured to provide the heat to reach the desired process temperature for the processing of the plurality of substrates. The vertical furnace may further comprise heat distributing member for distributing the heat provided by the heating element. Embodiments of the presently described method comprise processing the plurality of substrates in a vertical furnace described herein.

公开(公告)号：US20240068097A1

公开(公告)日：2024-02-29

申请号：US18452725

申请日：2023-08-21

Applicant: ASM IP Holding B.V.

Inventor： Subir Parui ,  Werner Knaepen ,  Dieter Pierreux ,  Kelly Houben ,  Herbert Terhorst ,  Theodorus G.M. Oosterlaken ,  Angelos Karagiannis

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/458 ,  C23C16/52

CPC classification number: C23C16/45574 ,  C23C16/4412 ,  C23C16/45546 ,  C23C16/4584 ,  C23C16/52

Abstract: A substrate processing apparatus configured to from a layer on a plurality of substrates is disclosed. Embodiments of the presently described substrate processing apparatus comprise a process chamber. The process chamber comprises process space for receiving a substrate boat arranged for holding the plurality of substrates. The substrate processing apparatus further comprise a gas delivery assembly comprising at least one gas injector; a gas exhaust assembly comprising two gas outlets. The two gas outlets are positioned at a distance on either side of the at least one gas injector.

公开(公告)号：US20230230833A1

公开(公告)日：2023-07-20

申请号：US18127201

申请日：2023-03-28

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H10B43/27

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H10B43/27

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US10453685B2

公开(公告)日：2019-10-22

申请号：US15476752

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Kelly Houben ,  Steven R. A. Van Aerde ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/311 ,  H01L21/033

Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.

公开(公告)号：US20240145262A1

公开(公告)日：2024-05-02

申请号：US18495323

申请日：2023-10-26

Applicant: ASM IP Holding B.V.

Inventor： Theodorus G.M. Oosterlaken ,  Kelly Houben ,  Herbert Terhorst ,  Cornelis Herbschleb

IPC: H01L21/67 ,  H01L21/02

CPC classification number: H01L21/67017 ,  H01L21/02277

Abstract: A gas injector assembly and a substrate processing apparatus comprising the gas injector assembly is disclosed. Embodiments of the presently described gas injector assembly comprise a gas injector, a first precursor gas supply conduit and a second precursor gas supply conduit. A size of the first precursor gas supply conduit is larger than the size of the second precursor gas supply conduit.