Dynamic configuration of memory timing parameters

    公开(公告)号:US11079945B2

    公开(公告)日:2021-08-03

    申请号:US16137413

    申请日:2018-09-20

    Abstract: A processing system includes a memory controller coupleable to a RAM, and a ROM configured to store boot information that includes default values for a set of one or more memory timing parameters. At least one processor is configured to, during initialization, configure the memory controller to utilize the default values for the set of one or more memory timing parameters. The at least one processor further is configured to, during operation of the processing system following initialization, receive user input representing one or more updated values for one or more corresponding memory timing parameters of the set, and to dynamically reconfigure the memory controller to utilize one or more updated values for the set of one or more memory timing parameters for the signaling. The processing system further is configured to conduct one or more memory access operations for the RAM using the reconfigured memory controller.

    ADAPTIVE POWER MANAGEMENT
    4.
    发明公开

    公开(公告)号:US20240248523A1

    公开(公告)日:2024-07-25

    申请号:US18628684

    申请日:2024-04-06

    CPC classification number: G06F1/3234

    Abstract: Techniques are described for adaptive device power management. The device interface application of a hardware computing unit detects a launch of an application by the operating system (OS) to be executed on the hardware computing unit, in an implementation. The device interface application identifies the launched application and determines whether a hardware profile exists that is associated with the application. The hardware profile includes one or more hardware parameters that yield the optimal performance for power consumption by the hardware computing unit when executing the launched application. Based on determining that the hardware profile exists, the power policy of the OS is updated for the launched application, and thereby, the driver updates the power state(s) of the hardware computing unit based on the new power policy.

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