-
公开(公告)号：US07272702B2
公开(公告)日：2007-09-18
申请号：US10702252
申请日：2003-11-06
IPC分类号： G06F9/34
CPC分类号： G06F9/30123 , G06F9/30134 , G06F9/384 , G06F9/3842 , G06F9/3861
摘要： Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault. The instruction execution unit executes the instruction is the instruction execution unit determines that the register is within the current register stack frame. When execution of the instruction requires reading from a register referenced by the instruction, the instruction execution unit executes the instruction whether or not the register referenced by the instruction is within the current register stack frame.
摘要翻译： 公开了用于管理对当前寄存器堆栈帧之外的寄存器的访问的方法和装置。 处理器中的指令执行单元接收要执行的指令。 处理器包括寄存器堆栈，寄存器堆栈包括多个寄存器堆栈帧。 每个寄存器堆栈帧包括零个或多个寄存器。 多个寄存器堆栈帧中的一个是当前寄存器堆栈帧。 当执行指令需要写入由指令引用的寄存器时，指令执行单元确定该指令引用的寄存器是否在当前寄存器堆栈帧内。 如果指令执行单元确定寄存器不在当前寄存器堆栈帧内，则指令执行单元不执行指令，并且例如可能产生故障。 指令执行单元执行指令是指令执行单元确定寄存器在当前寄存器堆栈帧内。 当指令的执行需要从指令引用的寄存器读取时，指令执行单元执行指令，该指令是否由指令引用的寄存器是否在当前寄存器堆栈帧内。
-
2.发明授权Code sequence for asynchronous backing store switch utilizing both the cover and LOADRS instructions 失效使用封面和LOADRS指令的异步后备存储开关的代码序列
公开(公告)号：US6112292A
公开(公告)日：2000-08-29
申请号：US64025
申请日：1998-04-21
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/30134
摘要： A computer implemented method for switching from an interrupted context to an interrupting context in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) that exchanges information, in one of instruction execution dependent and independent modes between the second portion and a storage area. The method includes the following steps: a state of the RSE of the interrupted context is preserved; a COVER instruction is issued; a first (BSPSTORE) pointer is preserved. The first pointer points to a location in the storage area, of the interrupted context, where a next register of the second portion is to be written; first pointer is written with a value corresponding to the interrupting context; and a second pointer (BSP) is preserved. The new first and second pointers in the interrupting context define the storage area of RS values associated with the interrupted context. The new first pointer is subtracted from the second new pointer. The difference (number of dirty registers) is deposited into the RSC.loadrs field. A LOADRS instruction is issued to load the RS with all interrupted context values. The original first BSPSTORE is restored from the preserved BSPSTORE.
摘要翻译： 提供了一种用于从中断的上下文切换到处理器中的中断上下文的计算机实现的方法。 处理器包括具有第一和第二部分的寄存器堆栈（RS）。 处理器包括在第二部分和存储区域之间以指令执行相关的和独立的模式之一交换信息的寄存器堆栈引擎（RSE）。 该方法包括以下步骤：保持中断上下文的RSE状态; 发出COVER指令; 第一个（BSPSTORE）指针被保留。 第一指针指向存储区域中断上下文的位置，其中第二部分的下一个寄存器将被写入; 第一个指针用与中断上下文相对应的值写入; 并保留第二个指针（BSP）。 中断上下文中的新的第一和第二指针定义与中断上下文相关联的RS值的存储区域。 从第二个新指针中减去新的第一个指针。 差异（脏寄存器数）被存入RSC.loadrs字段。 发出LOADRS指令以加载具有所有中断上下文值的RS。 原始的第一个BSPSTORE从保存的BSPSTORE恢复。
-
3.发明授权Method and apparatus for executing a flush RS instruction to synchronize a register stack with instructions executed by a processor 失效用于执行冲洗RS指令以使寄存器堆栈与由处理器执行的指令同步的方法和装置公开(公告)号：US06219783B1
公开(公告)日：2001-04-17
申请号：US09063737
申请日：1998-04-21
IPC分类号： G06F944
CPC分类号： G06F9/30127 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06F9/4484
摘要： A processor that is configured to execute a programmed flow of instructions is disclosed. The processor includes a register stack (RS). The register stack (RS) has a portion allocated for dirty registers. The processor also includes a register stack engine (RSE) to exchange information, in one of an instruction execution dependent and independent modes, between the RS and storage area. The processor also includes a flush control circuit to generate to the RSE, dependent of instruction execution a signal, in response to which, the RSE spills to the storage area all dirty registers, from the RS. A computer implemented method in a processor is also provided. The processor includes a register stack (RS) device that includes a portion allocated for dirty registers. The portion is defined by first and second physical register numbers. The processor further includes a register stack engine (RSE) to exchange information in one of an instruction execution dependent and independent modes between a storage area and the RS. The storage area is defined by first and second pointers. At step a, it is determined whether the first and second physical register numbers have a predetermined logical relationship relative to each other. At step b, it is stored by the RSE, a register of the portion of the RS to a first location in the storage area corresponding to the first pointer, if the first and second physical register numbers have a predetermined logical relationship relative to each other. At step c, it is pointed to a next location in the storage area and the first physical register number is incremented. Therefore, the RSE is synchronized with the instructions executed by the processor.
摘要翻译： 公开了一种被配置为执行编程的指令流的处理器。 处理器包括寄存器堆栈（RS）。 寄存器堆栈（RS）具有分配给脏寄存器的部分。 该处理器还包括一个寄存器堆栈引擎（RSE），用于在RS和存储区域之间以指令执行相关和独立模式之一交换信息。 该处理器还包括一个刷新控制电路，用于根据指令执行信号向RSE生成响应RSE的RSE向存储区域所有脏寄存器的响应。 还提供了处理器中的计算机实现的方法。 处理器包括寄存器堆栈（RS）设备，其包括分配给脏寄存器的部分。 该部分由第一和第二物理寄存器编号定义。 该处理器还包括一个寄存器堆栈引擎（RSE），用于以存储区域和RS之间的指令执行依赖和独立模式之一交换信息。 存储区域由第一和第二指针定义。 在步骤a中，确定第一和第二物理寄存器号码是否具有相对于彼此的预定逻辑关系。 在步骤b中，如果第一和第二物理寄存器号相对于彼此具有预定的逻辑关系，则由RSE存储RS的该部分的寄存器到与第一指针对应的存储区域中的第一位置 。 在步骤c中，指向存储区域中的下一个位置，并且增加第一物理寄存器号码。 因此，RSE与由处理器执行的指令同步。
-
公开(公告)号：US6065114A
公开(公告)日：2000-05-16
申请号：US64091
申请日：1998-04-21
申请人： Achmed Rumi Zahir , Jonathan K. Ross , Carol Thompson , Cary Coutant , Prasad Raje , Sunil Saxena
发明人： Achmed Rumi Zahir , Jonathan K. Ross , Carol Thompson , Cary Coutant , Prasad Raje , Sunil Saxena
CPC分类号： G06F9/4812 , G06F9/3009 , G06F9/30127 , G06F9/30134 , G06F9/4425 , G06F9/461
摘要： A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area. On return from interruption, if IFM is validated, CFM is restored from IFM else CFM remains unchanged. The COVER instruction enables lightweight interrupt handling in a processor with a Register Stack.
摘要翻译： 提供了一种在处理器中切换上下文的计算机实现的方法。 处理器包括具有第一和第二部分的寄存器堆栈（RS）。 该处理器包括一个寄存器堆栈引擎（RSE），用于在第二部分和存储区域之间以指令执行相关和独立模式之一交换信息。 计算机实现的切换上下文的方法包括以下步骤：确定是否发生中断; 配置为存储第二寄存器（CFM）的内容的第一寄存器（IFM）无效，所述CFM被配置为存储与所述第一部分相关的控制信息; 确定中断处理程序是否需要访问RS; 如果是，则IFM被验证，CFM的内容被复制到IFM，并且使RSE在RS的第一和第二部分与存储区域之间交换信息。 从中断返回时，如果IFM被验证，则从IFM恢复CFM，否则CFM保持不变。 COVER指令在具有寄存器堆栈的处理器中实现轻量级中断处理。
-
公开(公告)号：US06665793B1
公开(公告)日：2003-12-16
申请号：US09473820
申请日：1999-12-28
IPC分类号： G06F9312
CPC分类号： G06F9/30123 , G06F9/30134 , G06F9/384 , G06F9/3842 , G06F9/3861
摘要： Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault. The instruction execution unit executes the instruction is the instruction execution unit determines that the register is within the current register stack frame. When execution of the instruction requires reading from a register referenced by the instruction, the instruction execution unit executes the instruction whether or not the register referenced by the instruction is within the current register stack frame.
摘要翻译： 公开了用于管理对当前寄存器堆栈帧之外的寄存器的访问的方法和装置。 处理器中的指令执行单元接收要执行的指令。 处理器包括寄存器堆栈，寄存器堆栈包括多个寄存器堆栈帧。 每个寄存器堆栈帧包括零个或多个寄存器。 多个寄存器堆栈帧中的一个是当前寄存器堆栈帧。 当执行指令需要写入由指令引用的寄存器时，指令执行单元确定该指令引用的寄存器是否在当前寄存器堆栈帧内。 如果指令执行单元确定寄存器不在当前寄存器堆栈帧内，则指令执行单元不执行指令，并且例如可能产生故障。 指令执行单元执行指令是指令执行单元确定寄存器在当前寄存器堆栈帧内。 当指令的执行需要从指令引用的寄存器读取时，指令执行单元执行指令，该指令是否由指令引用的寄存器是否在当前寄存器堆栈帧内。
-
公开(公告)号：US07334112B2
公开(公告)日：2008-02-19
申请号：US10702355
申请日：2003-11-06
IPC分类号： G06F9/312
CPC分类号： G06F9/30123 , G06F9/30134 , G06F9/384 , G06F9/3842 , G06F9/3861
摘要： Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault. The instruction execution unit executes the instruction is the instruction execution unit determines that the register is within the current register stack frame. When execution of the instruction requires reading from a register referenced by the instruction, the instruction execution unit executes the instruction whether or not the register referenced by the instruction is within the current register stack frame.
摘要翻译： 公开了用于管理对当前寄存器堆栈帧之外的寄存器的访问的方法和装置。 处理器中的指令执行单元接收要执行的指令。 处理器包括寄存器堆栈，寄存器堆栈包括多个寄存器堆栈帧。 每个寄存器堆栈帧包括零个或多个寄存器。 多个寄存器堆栈帧中的一个是当前寄存器堆栈帧。 当执行指令需要写入由指令引用的寄存器时，指令执行单元确定该指令引用的寄存器是否在当前寄存器堆栈帧内。 如果指令执行单元确定寄存器不在当前寄存器堆栈帧内，则指令执行单元不执行指令，并且例如可能产生故障。 指令执行单元执行指令是指令执行单元确定寄存器在当前寄存器堆栈帧内。 当指令的执行需要从指令引用的寄存器读取时，指令执行单元执行指令，该指令是否由指令引用的寄存器是否在当前寄存器堆栈帧内。
-
7.发明授权System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch 失效用于在状态保存上下文切换期间同步寄存器堆栈引擎（RSE）和备份存储器映像与处理器执行指令的系统和方法公开(公告)号：US06367005B1
公开(公告)日：2002-04-02
申请号：US09677617
申请日：2000-10-02
IPC分类号： G06F948
CPC分类号： G06F9/30127 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06F9/4484
摘要： A computer implemented method in a processor to perform a backing store switch from a first context (source context) to a second context (target context) is provided whereby the backing store memory image and RSE will be synchronized with the processor's execution of instructions. The processor includes a register stack (RS) device that includes a portion allocated for dirty registers. The portion is defined by first and second physical register numbers. The processor further includes a register stack engine (RSE) to exchange information in one of an instruction execution dependent and independent modes between a storage area and the RS. The processor further includes a FLUSHRS state machine to notify the RSE to store dirty register in the RS to a backing store located in a memory.
摘要翻译： 提供了一种用于执行从第一上下文（源上下文）到第二上下文（目标上下文）的后备存储切换的处理器中的计算机实现的方法，由此后备存储存储器映像和RSE将与处理器的指令执行同步。 处理器包括寄存器堆栈（RS）设备，其包括分配给脏寄存器的部分。 该部分由第一和第二物理寄存器编号定义。 该处理器还包括一个寄存器堆栈引擎（RSE），用于以存储区域和RS之间的指令执行依赖和独立模式之一交换信息。 处理器还包括FLUSHRS状态机，以通知RSE将RS中的脏寄存器存储到位于存储器中的后备存储器。
-
公开(公告)号：US6115777A
公开(公告)日：2000-09-05
申请号：US63739
申请日：1998-04-21
CPC分类号： G06F9/4812 , G06F13/24 , G06F9/3009 , G06F9/30134 , G06F9/3861 , G06F9/461
摘要： A method for returning from an interrupting context to an interrupted context in a processor is disclosed. The processor executes a programmed flow of instructions. The processor includes a register stack (RS) and a register stack engine (RSE) to exchange information between the RS and the storage area. The method includes the following steps: (a.) A first pointer (PTR) is generated. The pointer (PTR) points to a location in the storage area where dirty registers (previously unsaved) of an interrupted context are stored; (b.) It is determined whether a mathematical relation is valid between the first pointer and the second pointer (BSPLOAD) to a location in the storage area from where the RSE is configured to load dirty register values into the RS; (c) The second pointer is caused to point to a next location in the storage area if the relation is valid; and (d) A register of the RS is loaded with a content of the next location in the storage area until the mathematical relation becomes invalid.
摘要翻译： 公开了一种用于在处理器中从中断上下文返回到中断的上下文的方法。 处理器执行编程的指令流程。 处理器包括寄存器堆栈（RS）和寄存器堆栈引擎（RSE），以在RS和存储区域之间交换信息。 该方法包括以下步骤：（a。）生成第一个指针（PTR）。 指针（PTR）指向存储区域中存在中断上下文的脏寄存器（以前未保存）的位置; （b。）确定第一指针和第二指针（BSPLOAD）之间的数学关系是否与存储区域中的RSE被配置为将脏寄存器值加载到RS中的位置有关; （c）如果关系有效，第二个指针指向存储区域中的下一个位置; 和（d）RS的寄存器被加载在存储区域中的下一个位置的内容，直到数学关系变得无效。
-
9.发明授权Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes 失效具有用于分别存储用于多个处理器节点的TLB击落数据的多个存储器位置的多处理器系统公开(公告)号：US07281116B2
公开(公告)日：2007-10-09
申请号：US10903200
申请日：2004-07-30
申请人： Jonathan K. Ross , Dale Morris
发明人： Jonathan K. Ross , Dale Morris
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/682
摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.
摘要翻译： 本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。 与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。 因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。
-
公开(公告)号：US07613847B2
公开(公告)日：2009-11-03
申请号：US11435831
申请日：2006-05-16
CPC分类号： G06F12/1081 , G06F9/45558 , G06F2009/45579 , H04L67/08
摘要： A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system adapted to control the physical computer. The computer system further comprises a host executable on the physical computer that manages physical resources coupled to the physical computer on behalf of the virtual machine monitor and the at least one guest operating system. The host is adapted to virtualize a Peripheral Component Interconnect (PCI) configuration address space whereby the at least one guest operating system controls PCI input/output (I/O) devices directly and in absence of I/O emulation.
摘要翻译： 计算机系统包括物理计算机和可在物理计算机上执行的虚拟机监视器，并且被配置为创建适于控制物理计算机的至少一个客户操作系统的仿真。 计算机系统还包括在物理计算机上可执行的主机，其代表虚拟机监视器和至少一个客户操作系统管理耦合到物理计算机的物理资源。 主机适于虚拟化外围组件互连（PCI）配置地址空间，由此至少一个客户操作系统直接控制PCI输入/输出（I / O）设备，并且在没有I / O仿真的情况下。
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.017 秒)