公开(公告)号：US06417526B2

公开(公告)日：2002-07-09

申请号：US09288395

申请日：1999-04-08

申请人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Michael S. Peter ,  Hendrik G. A. Huizing ,  Wiebe B. De Boer

发明人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Michael S. Peter ,  Hendrik G. A. Huizing ,  Wiebe B. De Boer

IPC分类号： H01L29861

CPC分类号： H01L29/885 ,  H01L29/32 ,  Y10S438/979

摘要： The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.

摘要翻译： 本发明涉及一种半导体器件，其具有位于相反导电型的两个（半导体）区域（1,2）之间的整流结（5）。 包括硅的第二区域（2）比第一区域（1）更厚并且具有更小的掺杂浓度，该第一区域包括包含硅和锗的混合晶体的子区域。 两个区域（1,2）各自设置有连接导体（3,4）。 这种装置可以非常适合地用作开关元件，特别是用作高电压和/或高功率的开关元件。 在已知的器件中，硅 - 锗混晶被放宽，导致失配位错的形成。 这些用于减少少数电荷载体的使用寿命，从而使装置能够非常快地切换。 在根据本发明的装置中，整个第一区域（1）包括硅和锗的混合晶体，并且选择锗含量和第一区域（1）的厚度，使得在半导体中积聚的电压 器件仍然低于发生错配位错的水平。 令人惊讶的是，已经发现，这种装置也可以非常快速地切换，甚至比已知装置更快地切换。 没有错配位错具有额外的优点，即该装置非常可靠。 如果晶格常数相对偏差和第一区域的厚度的乘积小于或等于40nm％，则不会发生失配位错。 所述产品的安全上限为30nm％。

公开(公告)号：US06459133B1

公开(公告)日：2002-10-01

申请号：US09545782

申请日：2000-04-07

申请人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Hendrik G. A. Huizing ,  Eddie Huang

发明人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Hendrik G. A. Huizing ,  Eddie Huang

IPC分类号： H01L2358

CPC分类号： H01L29/8618

摘要： The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2). It has been found that the high current at a low voltage of the known diode is caused by the fact that the second semiconductor region (2) at the edge of the mesa (12) is depleted before the remainder of the second semiconductor region (2). By locally increasing the flux of doping atoms, the depletion at the edge is delayed as compared to the remainder of the second semiconductor region. Preferably, this result is obtained by locally increasing the thickness of the second semiconductor region (2). In this manner, a substantial current reduction at lower voltages is obtained in the diode in accordance with the invention.

摘要翻译： 本发明涉及一种所谓的穿通二极管，其具有台面（12），它们分别包括第一（1），第二（2）和第三（3）半导体区域（1） 第一和第二导电类型，该穿通二极管设置有两个连接导体（5,6）。 在所述二极管的操作期间，施加电压使得第二半导体区域（2）完全耗尽。 已知的穿通二极管的缺点在于电流在较低的电压下太大。 在根据本发明的穿通二极管中，第二半导体区域（2）的一部分（2A，2B）在投影面上与台面（12）的边缘相邻地设置有较大的通量 的第二导电类型的掺杂原子比第二半导体区域（2）的其余部分（2A）。 已经发现，已知二极管的低电压下的高电流是由于在第二半导体区域（2）的剩余部分之前在台面（12）的边缘处的第二半导体区域（2）被耗尽的事实引起的， ）。 通过局部增加掺杂原子的通量，与第二半导体区域的剩余部分相比，边缘处的耗尽被延迟。 优选地，通过局部增加第二半导体区域（2）的厚度来获得该​​结果。 以这种方式，在根据本发明的二极管中获得在较低电压下的实质电流降低。

公开(公告)号：US07660180B2

公开(公告)日：2010-02-09

申请号：US11720320

申请日：2005-11-24

申请人： Hans M. B. Boeve ,  Karen Attenborough ,  Godefridus A. M. Hurkx ,  Prabhat Agarwal ,  Hendrik G. A. Huizing ,  Michael A. A. In'T Zandt ,  Jan W. Slotboom

发明人： Hans M. B. Boeve ,  Karen Attenborough ,  Godefridus A. M. Hurkx ,  Prabhat Agarwal ,  Hendrik G. A. Huizing ,  Michael A. A. In'T Zandt ,  Jan W. Slotboom

IPC分类号： G11C17/18

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.

摘要翻译： 热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。 这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径， 用作编程材料的微小电加热器。 由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。 因此，编程功率可能很低。

公开(公告)号：US07923339B2

公开(公告)日：2011-04-12

申请号：US11721033

申请日：2005-11-29

申请人： Philippe Meunier-Beillard ,  Hendrik G. A. Huizing

发明人： Philippe Meunier-Beillard ,  Hendrik G. A. Huizing

IPC分类号： H01L21/336

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/31662 ,  Y10S438/916

摘要： The invention relates to the manufacture of an epitaxial layer, with the following steps: providing a semiconductor substrate; providing a Si—Ge layer on the semiconductor substrate, having a first depth; —providing the semiconductor substrate with a doped layer with an n-type dopant material and having a second depth substantially greater than said first depth; performing an oxidation step to form a silicon dioxide layer such that Ge atoms and n-type atoms are pushed into the semiconductor substrate by the silicon dioxide layer at the silicon dioxide/silicon interface, wherein the n-type atoms are pushed deeper into the semiconductor substrate than the Ge atoms, resulting in a top layer with a reduced concentration of n-type atoms; removing the silicon dioxide layer; growing an epitaxial layer of silicon on the semiconductor substrate with a reduced outdiffusion or autodoping.

摘要翻译： 本发明涉及外延层的制造，其步骤如下：提供半导体衬底; 在所述半导体衬底上提供具有第一深度的Si-Ge层; - 用具有n型掺杂剂材料的掺杂层提供半导体衬底并且具有基本上大于所述第一深度的第二深度; 进行氧化步骤以形成二氧化硅层，使得Ge原子和n型原子通过二氧化硅/硅界面处的二氧化硅层被推入半导体衬底，其中n型原子被更深地推入半导体 底物比Ge原子，导致顶层具有降低的n型原子浓度; 去除二氧化硅层; 在半导体衬底上生长硅外延层，其外延扩散或自动掺杂。

公开(公告)号：US07911822B2

公开(公告)日：2011-03-22

申请号：US11577708

申请日：2005-10-17

申请人： Martijn H. R. Lankhorst ,  Hendrik G. A. Huizing

发明人： Martijn H. R. Lankhorst ,  Hendrik G. A. Huizing

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C13/0004

摘要： The present invention relates to an integrated circuit comprising a plurality of bitlines (b1) and a plurality of word-lines (w1) as well as a plurality of memory-cells (MC) coupled between a separate bit-line/word-line pair of the plurality of bit-lines (b1) and wordlines (w1) for storing data in the memory cell. Each memory cell (MC) comprises a selecting unit (T) and a programmable resistance (R). The value of the phase-change resistance (R) is greater than the value of a first phase-change resistance (Ropt) defined by a supply voltage (Vdd) divided by a maximum drive current (Im) through said first phase-change resistor (Ropt).

摘要翻译： 本发明涉及一种集成电路，其包括多个位线（b1）和多个字线（w1）以及耦合在单独的位线/字线对之间的多个存储单元（MC） 用于将数据存储在存储单元中的多个位线（b1）和字线（w1）。 每个存储单元（MC）包括选择单元（T）和可编程电阻（R）。 相位变化电阻（R）的值大于由电源电压（Vdd）除以通过所述第一相变电阻器的最大驱动电流（Im）所限定的第一相变电阻（Ropt）的值 （Ropt）。