公开(公告)号：US06459133B1

公开(公告)日：2002-10-01

申请号：US09545782

申请日：2000-04-07

申请人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Hendrik G. A. Huizing ,  Eddie Huang

发明人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Hendrik G. A. Huizing ,  Eddie Huang

IPC分类号： H01L2358

CPC分类号： H01L29/8618

摘要： The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2). It has been found that the high current at a low voltage of the known diode is caused by the fact that the second semiconductor region (2) at the edge of the mesa (12) is depleted before the remainder of the second semiconductor region (2). By locally increasing the flux of doping atoms, the depletion at the edge is delayed as compared to the remainder of the second semiconductor region. Preferably, this result is obtained by locally increasing the thickness of the second semiconductor region (2). In this manner, a substantial current reduction at lower voltages is obtained in the diode in accordance with the invention.

摘要翻译： 本发明涉及一种所谓的穿通二极管，其具有台面（12），它们分别包括第一（1），第二（2）和第三（3）半导体区域（1） 第一和第二导电类型，该穿通二极管设置有两个连接导体（5,6）。 在所述二极管的操作期间，施加电压使得第二半导体区域（2）完全耗尽。 已知的穿通二极管的缺点在于电流在较低的电压下太大。 在根据本发明的穿通二极管中，第二半导体区域（2）的一部分（2A，2B）在投影面上与台面（12）的边缘相邻地设置有较大的通量 的第二导电类型的掺杂原子比第二半导体区域（2）的其余部分（2A）。 已经发现，已知二极管的低电压下的高电流是由于在第二半导体区域（2）的剩余部分之前在台面（12）的边缘处的第二半导体区域（2）被耗尽的事实引起的， ）。 通过局部增加掺杂原子的通量，与第二半导体区域的剩余部分相比，边缘处的耗尽被延迟。 优选地，通过局部增加第二半导体区域（2）的厚度来获得该​​结果。 以这种方式，在根据本发明的二极管中获得在较低电压下的实质电流降低。

公开(公告)号：US06417526B2

公开(公告)日：2002-07-09

申请号：US09288395

申请日：1999-04-08

申请人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Michael S. Peter ,  Hendrik G. A. Huizing ,  Wiebe B. De Boer

发明人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Michael S. Peter ,  Hendrik G. A. Huizing ,  Wiebe B. De Boer

IPC分类号： H01L29861

CPC分类号： H01L29/885 ,  H01L29/32 ,  Y10S438/979

摘要： The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.

摘要翻译： 本发明涉及一种半导体器件，其具有位于相反导电型的两个（半导体）区域（1,2）之间的整流结（5）。 包括硅的第二区域（2）比第一区域（1）更厚并且具有更小的掺杂浓度，该第一区域包括包含硅和锗的混合晶体的子区域。 两个区域（1,2）各自设置有连接导体（3,4）。 这种装置可以非常适合地用作开关元件，特别是用作高电压和/或高功率的开关元件。 在已知的器件中，硅 - 锗混晶被放宽，导致失配位错的形成。 这些用于减少少数电荷载体的使用寿命，从而使装置能够非常快地切换。 在根据本发明的装置中，整个第一区域（1）包括硅和锗的混合晶体，并且选择锗含量和第一区域（1）的厚度，使得在半导体中积聚的电压 器件仍然低于发生错配位错的水平。 令人惊讶的是，已经发现，这种装置也可以非常快速地切换，甚至比已知装置更快地切换。 没有错配位错具有额外的优点，即该装置非常可靠。 如果晶格常数相对偏差和第一区域的厚度的乘积小于或等于40nm％，则不会发生失配位错。 所述产品的安全上限为30nm％。

公开(公告)号：US06242762B1

公开(公告)日：2001-06-05

申请号：US09078231

申请日：1998-05-13

申请人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Jan W. Slotboom

发明人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Jan W. Slotboom

IPC分类号： H01L29861

CPC分类号： H01L29/885 ,  Y10S438/979

摘要： A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (2A, 3A) of the semiconductor regions (2, 3) adjoining the junction (23) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (2, 3). The tunnelling efficiency is substantially improved as a result of this, and also because of the reduced bandgap of said portions (2A, 3A), and the device according to the invention has a much steeper current-voltage characteristic both in the forward and in the reverse direction. This opens perspectives for inter alia an attractive application where the tunnelling pn junction (23) is used as a transition between two conventional diodes, for example pn or pin diodes, which are used one stacked on the other and which can be formed in a single epitaxial growing process thanks to the invention. The portions (2A, 3A) adjoining the tunnelling junction (22) are preferably 5 to 30 nm thick and comprise between 10 and 50 at % germanium. The doping concentration may be 6×1019 or even more than 1020 at/cm3. The invention further relates to a simple method of manufacturing a device according to the invention. This is preferably done at a temperature of between 550° C. and 800° C.

公开(公告)号：US06436785B1

公开(公告)日：2002-08-20

申请号：US09832724

申请日：2001-04-11

申请人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Jan W. Slotboom

发明人： Adam R. Brown ,  Godefridus A. M. Hurkx ,  Wiebe B. De Boer ,  Jan W. Slotboom

IPC分类号： H01L2120

摘要： A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3. A simple method of manufacturing such a device is preferably done at a temperature between 550° C. and 800° C.

公开(公告)号：US06331467B1

公开(公告)日：2001-12-18

申请号：US09538467

申请日：2000-03-29

申请人： Adam R. Brown ,  Raymond J. E. Hueting ,  Godefridus A. M. Hurkx

发明人： Adam R. Brown ,  Raymond J. E. Hueting ,  Godefridus A. M. Hurkx

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/165 ,  H01L29/66348 ,  H01L29/7397 ,  Y10S438/97

摘要： A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

摘要翻译： 半导体本体（1）具有通过相反导电类型的第二半导体区域（5）与第一主表面（5a）分离的一种导电类型的第一半导体区域（3）。 通过使用蚀刻工艺将沟槽（7）通过第二半导体区域（5）蚀刻到设置在第一（3）和第二（5）区域之间的pn结区域中的蚀刻停止层（4），其中 使蚀刻工艺在蚀刻停止层处停止。 在沟槽（7）内设有一个门（8,9）。 与沟槽相邻地形成与第一区域（3）分离的源极（12），使得邻近沟槽的第二区域（5）的导电通道区域（50）提供在第二区域 源极和第一区域，其可由栅极控制。

公开(公告)号：US06218222B1

公开(公告)日：2001-04-17

申请号：US09141644

申请日：1998-08-27

申请人： Adam R. Brown ,  Wiebe B. De Boer

发明人： Adam R. Brown ,  Wiebe B. De Boer

IPC分类号： H01L21338

CPC分类号： H01L29/66143 ,  H01L29/872

摘要： Devices with Schottky junctions are manufactured in that a semiconductor body with a substrate is provided with a first, for example n-type semiconductor region in the form of an epitaxial layer. A Schottky metal is locally provided thereon. A second semiconductor region is advantageously formed directly below the Schottky metal, with the purpose of adjusting the level of the Schottky barrier. Around this, a third semiconductor region is formed in the first region at at least two sides, which third region is then of the p-conductivity type and, when it entirely surrounds the second region, forms a so-called guard ring. A disadvantage of the above known method is that the devices obtained thereby have a (forward) current-voltage characteristic which is not very well controllable and reproducible. This hampers mass manufacture. To counteract this disadvantage, a method according to the invention provides the formation of the second semiconductor region by means of low-temperature gas phase epitaxy, such that it has the first or the second conductivity type, and the third region is formed by means of ion implantation, the second semiconductor region being formed after the third region has been formed. Devices are obtained thereby whose current-voltage characteristics can be adjusted over a wide range with very good reproducibility and well controlled. The second semiconductor region may be provided over the entire surface or selectively within the third region only.

摘要翻译： 具有肖特基结的器件的制造方式是具有衬底的半导体本体设置有外延层形式的第一例如n型半导体区域。 本地提供肖特基金属。 为了调整肖特基势垒的水平，第二半导体区域有利地直接形成在肖特基金属的正下方。 围绕这一点，第三半导体区域形成在至少两侧的第一区域中，该第三区域然后是p导电型，并且当其完全包围第二区域时，形成所谓的保护环。 上述已知方法的缺点在于所获得的器件具有不是非常好的可控性和可再现性的（正向）电流 - 电压特性。 这妨碍了批量生产。 为了抵消这个缺点，根据本发明的方法提供了通过低温气相外延形成第二半导体区域，使得其具有第一或第二导电类型，并且第三区域通过 离子注入，第二半导体区域形成在第三区域形成之后。 从而可以获得电流电压特性可以在很宽的范围内进行调节，具有很好的再现性和良好的控制性。 第二半导体区域可以仅设置在整个表面上或仅在第三区域内选择性地设置。

公开(公告)号：US5425125A

公开(公告)日：1995-06-13

申请号：US199036

申请日：1994-02-18

申请人： Andrew B. Holmes ,  Donal D. Bradley ,  Richard H. Friend ,  Paul L. Burn ,  Arno Kraft ,  Adam R. Brown

发明人： Andrew B. Holmes ,  Donal D. Bradley ,  Richard H. Friend ,  Paul L. Burn ,  Arno Kraft ,  Adam R. Brown

IPC分类号： C08G61/02 ,  C07C43/205 ,  C07C43/225 ,  C08G61/00 ,  C08G61/10 ,  C08G61/12 ,  C09K11/06 ,  H01B1/12 ,  H01L33/00 ,  H01L51/00 ,  H01L51/30 ,  H01L51/50 ,  H01L51/56 ,  H05B33/10 ,  H05B33/12 ,  H05B33/14 ,  G02B6/10

CPC分类号： H05B33/14 ,  C07C43/2055 ,  C07C43/225 ,  C08G61/00 ,  C09K11/06 ,  H01B1/127 ,  H01B1/128 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0043 ,  H01L51/5012 ,  H01L51/5036 ,  H01L51/56 ,  Y10T428/3158 ,  Y10T428/31587 ,  Y10T428/31645

摘要： A method is provided for forming in a semiconductive conjugated polymer at least first and second legions having different optical properties. The method comprises: forming a layer of a precursor polymer and permitting the first region to come into contact with a reactant, such as an acid, and heat while permitting the second region to come into contact with a lower concentration of the reactant. The reactant affects the conversion conditions of the precursor polymer in such a way as to control the optical properties of at least the first region so that the optical properties of the first region are different from those of the second region. The precursor polymer may comprise a poly(arylene-1, 2-ethanediyl) polymer, at least some of the ethane groups of which include a modifier group whose susceptibility to elimination is increased in the presence of the reactant.

摘要翻译： 提供一种在半导体共轭聚合物中形成具有不同光学特性的至少第一和第二团粒的方法。 该方法包括：形成前体聚合物层，并允许第一区域与反应物（例如酸）​​接触并加热，同时允许第二区域与较低浓度的反应物接触。 反应物以这样的方式影响前体聚合物的转化条件，以便控制至少第一区域的光学性质，使得第一区域的光学性质与第二区域的光学性质不同。 前体聚合物可以包含聚（亚芳基-1,2-乙二基）聚合物，其中至少一些乙烷基团包括在反应物存在下易于消除的易感性的改性剂基团。

公开(公告)号：US20090236659A1

公开(公告)日：2009-09-24

申请号：US12299917

申请日：2007-05-02

申请人： Mark A. Gajda ,  Ian Kennedy ,  Adam R. Brown ,  James B. Parkin

发明人： Mark A. Gajda ,  Ian Kennedy ,  Adam R. Brown ,  James B. Parkin

IPC分类号： H01L29/78 ,  H01L21/77 ,  H01L21/762

CPC分类号： H01L29/7813 ,  H01L21/765 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7815

摘要： A semiconductor device has a first region (10) and a second region (20), gate trenches (50) being formed in paid first and second regions including insulated gates to control conduction between source regions (42) and a common drain region (40) through a body region separated into first (34) and second (36) body regions. Isolation between the first and second regions is provided in a simple way by providing a gap between the first and second body regions (34,36) formed by eg. at least one trench (52) or a part of the drain region.

摘要翻译： 半导体器件具有第一区域（10）和第二区域（20），栅极沟槽（50）形成在具有绝缘栅极的付费第一和第二区域中，以控制源极区域（42）和公共漏极区域（40）之间的导通 ）通过分离成第一（34）和第二（36）体区的体区。 以简单的方式提供第一和第二区域之间的隔离，通过在由第一和第二区域之间形成的第一和第二体区域（34,36）之间提供间隙。 至少一个沟槽（52）或漏极区域的一部分。

公开(公告)号：US06586800B2

公开(公告)日：2003-07-01

申请号：US09854395

申请日：2001-05-11

申请人： Adam R. Brown

发明人： Adam R. Brown

IPC分类号： H01L3162

CPC分类号： H01L29/1095 ,  H01L21/2257 ,  H01L29/0847 ,  H01L29/7813 ,  H01L29/7828

摘要： A trench-gate MOSFET or ACCUFET has its gate (21) in a first trench (20) that extends through a channel-accommodating body region (15) to a drain region (14). Within the transistor cells, a second trench (40) comprising deposited highly-doped semiconductor material (41) extends to the drain region (14). This highly-doped material (41) is of opposite conductivity type to the drain region (14) and, together with a possible out-diffusion profile (42), forms a localized region (41, 42) that is separated from the first trench (20) by the body region 15. A source electrode (23) contacts the source region (13) and the whole top area of the localized region (41, 42). In a MOSFET, the localized region (41, 42) provides protection against turning on of the cell's parasitic bipolar transistor. In an ACCUFET (FIG. 9), the localized region (41, 42) depletes the channel-accommodating body region (15A). In both devices the localized region (41, 42) is well-defined and can be narrow to enable a small transistor cell size. Furthermore, before filling the second trench (40) with its semiconductor material (41), the drain region (14) can be readily provided with an avalanche-breakdown region (64) at the bottom of the second trench (40), for example by implanting dopant ions (60) of the same conductivity type as the drain region (14). This avalanche-breakdown region (64) improves the ruggedness of the device. It can also aid current spreading (66) in the drain region (14) in the conductive state of the transistor.

摘要翻译： 沟槽栅极MOSFET或ACCUFET在其通过沟道容纳体区域（15）延伸到漏极区域（14）的第一沟槽（20）中具有栅极（21）。 在晶体管单元内，包括沉积的高掺杂半导体材料（41）的第二沟槽（40）延伸到漏区（14）。 该高掺杂材料（41）与漏区（14）具有相反的导电类型，并且与可能的外扩散分布（42）一起形成与第一沟槽分离的局部区域（41,42） （20）。源电极（23）接触源区域（13）和局部区域（41,42）的整个顶部区域。 在MOSFET中，局部区域（41,42）提供了防止电池的寄生双极晶体管导通的保护。 在ACCUFET（图9）中，局部区域（41,42）耗尽通道容纳体区域（15A）。 在两个器件中，局部区域（41,42）是明确限定的并且可以是窄的以使得能够实现小的晶体管单元尺寸。 此外，在用其半导体材料（41）填充第二沟槽（40）之前，漏极区域（14）可以容易地在第二沟槽（40）的底部设置有雪崩击穿区域（64），例如 通过注入与漏区（14）相同的导电类型的掺杂剂离子（60）。 这种雪崩击穿区域（64）提高了设备​​的坚固性。 还可以在晶体管的导通状态下帮助在漏区（14）中的电流扩展（66）。

公开(公告)号：US06528815B1

公开(公告)日：2003-03-04

申请号：US08798679

申请日：1997-02-12

申请人： Adam R. Brown ,  Dagobert M. De Leeuw ,  Edsko E. Havinga ,  Colin P. Jarrett

发明人： Adam R. Brown ,  Dagobert M. De Leeuw ,  Edsko E. Havinga ,  Colin P. Jarrett

IPC分类号： H01L2943

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  H01L27/28 ,  H01L51/0036 ,  H01L51/0037

摘要： The invention relates to a write-once read-many memory element (1), or an assembly thereof, which comprises a substrate on which electrodes are provided and between which a layer is sandwiched, which memory element includes a conjugated polymer or oligomer as well as a dopant. This memory element can be written by temporarily applying a sufficiently high voltage to the electrodes so that the electroconductivity of the layer is permanently reduced.

摘要翻译： 本发明涉及一次写入多次的只读存储元件（1）或其组件，其包括其上设置有电极的衬底，并且在其之间夹有层，该存储元件还包括共轭聚合物或低聚物 作为掺杂剂。 可以通过向电极施加足够高的电压来写入该存储元件，使得该层的导电性永久地减小。