公开(公告)号：US20080032462A1

公开(公告)日：2008-02-07

申请号：US11879424

申请日：2007-07-17

申请人： Adrian Cogan ,  Jin Qiu ,  Richard Blanchard

发明人： Adrian Cogan ,  Jin Qiu ,  Richard Blanchard

IPC分类号： H01L21/329

CPC分类号： H01L29/66136 ,  H01L27/0255 ,  H01L29/861

摘要： A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

摘要翻译： 两端势垒控制TVS二极管具有消耗区域阻挡阻挡多数载流子流过阴极区附近的沟道区域，该偏压电平低于施加在阳极电极和阴极电极之间的预定钳位电压的偏置电平，并且可布置 使得阳极区域在半导体结构的导通期间通过将少数载流子注入沟道区域来提供导电性调制。 在目前优选的形式中，多数载流子是电子，而少数载流子是空穴。 描述制造方法。

公开(公告)号：US20060131605A1

公开(公告)日：2006-06-22

申请号：US11020507

申请日：2004-12-22

申请人： Adrian Cogan ,  Jin Qiu ,  Richard Blanchard

发明人： Adrian Cogan ,  Jin Qiu ,  Richard Blanchard

IPC分类号： H01L29/74 ,  H01L23/62

CPC分类号： H01L29/66136 ,  H01L27/0255 ,  H01L29/861

摘要： A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

公开(公告)号：US08234392B2

公开(公告)日：2012-07-31

申请号：US11601497

申请日：2006-11-17

申请人： Peter Graffagnino ,  Dave Hyatt ,  Richard Blanchard ,  Kevin Calhoun ,  Gilles Drieu ,  Maciej Stachowiak ,  Don Melton ,  Darin Adler

发明人： Peter Graffagnino ,  Dave Hyatt ,  Richard Blanchard ,  Kevin Calhoun ,  Gilles Drieu ,  Maciej Stachowiak ,  Don Melton ,  Darin Adler

IPC分类号： G06F15/16

CPC分类号： G06T1/20 ,  G06F17/2205 ,  G06F17/2229 ,  G06F17/2247 ,  G06T11/00

摘要： Methods and apparatuses for providing hardware acceleration of a web browser are disclosed. In one embodiment, a method of operating a web browser on a computer system includes analyzing a data stream having a plurality of fragments. The method further includes determining what fragments of the data stream should be rendered for storage into separate backing stores. The method further includes rendering the fragments into raster images intended for hardware acceleration. The method further includes storing the raster images in the backing stores located in a graphics processing unit.

摘要翻译： 公开了一种用于提供网络浏览器的硬件加速的方法和装置。 在一个实施例中，在计算机系统上操作web浏览器的方法包括分析具有多个片段的数据流。 该方法还包括确定数据流的哪些片段应被呈现以用于存储到单独的后备存储中。 该方法还包括将片段渲染成用于硬件加速的光栅图像。 该方法还包括将光栅图像存储在位于图形处理单元中的后备存储器中。

公开(公告)号：US20050001272A1

公开(公告)日：2005-01-06

申请号：US10827676

申请日：2004-04-19

申请人： Richard Blanchard

发明人： Richard Blanchard

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/94

CPC分类号： H01L29/0692 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1087

摘要： A MOSFET device design is provided that effectively addresses the problems arising from the parasitic bipolar transistor that is intrinsic to the device. The MOSFET device comprises: (a) a body region; (b) a plurality of body contact regions; (c) a plurality of source regions; (d) a plurality of drain regions; and (d) a gate region. In plan view, the source regions and the drain regions are arranged in orthogonal rows and columns, and at least a portion of the body contact regions are bordered by four of the source and drain regions, preferably two source regions and two drain regions.

摘要翻译： 提供了MOSFET器件设计，可有效地解决由器件固有的寄生双极晶体管产生的问题。 MOSFET器件包括：（a）体区; （b）多个身体接触区域; （c）多个源区; （d）多个漏极区域; 和（d）栅极区域。 在平面图中，源极区域和漏极区域以正交的行和列布置，并且身体接触区域的至少一部分被源极和漏极区域中的四个区隔开，优选地是两个源极区域和两个漏极区域。

公开(公告)号：US09282219B2

公开(公告)日：2016-03-08

申请号：US13310220

申请日：2011-12-02

申请人： Howard A. Miller ,  Richard Blanchard ,  Todd W. Ritland

发明人： Howard A. Miller ,  Richard Blanchard ,  Todd W. Ritland

IPC分类号： H04N1/60 ,  G06K15/02 ,  H04N1/56 ,  H04N1/46

CPC分类号： H04N1/56 ,  H04N1/46

摘要： The disclosed embodiments provide a system that performs a print job. During operation, the system obtains one or more available media attributes, including a media size, a border size, and/or a media type, from a printer associated with the print job. Next, the system provides the available media attributes to an application and uses the application to automatically generate and format print data for the print job based on the available media attributes. Finally, the system sends the print job to the printer, where the print job is executed using the printer.

摘要翻译： 所公开的实施例提供执行打印作业的系统。 在操作期间，系统从与打印作业相关联的打印机获得一个或多个可用媒体属性，包括媒体大小，边框大小和/或媒体类型。 接下来，系统向应用程序提供可用的媒体属性，并使用应用程序根据可用的媒体属性自动生成和格式化打印作业的打印数据。 最后，系统将打印作业发送到使用打印机执行打印作业的打印机。

公开(公告)号：US20070012999A1

公开(公告)日：2007-01-18

申请号：US11534343

申请日：2006-09-22

申请人： Richard Blanchard

发明人： Richard Blanchard

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7802 ,  B82Y10/00 ,  H01L21/823807 ,  H01L29/0873 ,  H01L29/1054 ,  H01L29/152 ,  H01L29/155 ,  H01L29/158 ,  H01L29/66568 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7816

摘要： A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one nonsemiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

摘要翻译： 一种用于制造半导体器件的方法，其可以包括提供其中具有多个间隔开的超晶格的衬底，以及在衬底中形成源极和漏极区域，在衬底中限定沟道区域，以及沟道中的多个间隔开的超晶格和/或 漏区。 每个超晶格可以包括多个堆叠的层组，每个组包括限定基极半导体部分和至少一个非半导体单层的多个堆叠的基底半导体单层。 此外，至少一个非半导体单层可以被约束在相邻的基底半导体部分的晶格内。

公开(公告)号：US20060249788A1

公开(公告)日：2006-11-09

申请号：US11475640

申请日：2006-06-27

申请人： Richard Blanchard

发明人： Richard Blanchard

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/2255 ,  H01L21/2257 ,  H01L22/26 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66712

摘要： A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

公开(公告)号：US20060008937A1

公开(公告)日：2006-01-12

申请号：US10886435

申请日：2004-07-07

申请人： Richard Blanchard ,  Richard Robinson

发明人： Richard Blanchard ,  Richard Robinson

IPC分类号： H01L21/00

CPC分类号： H01L27/14645 ,  H01L27/14647 ,  H01L27/14683 ,  H01L27/14689

摘要： A multilayer color-sensing photodetector is fabricated in a semiconductor wafer having a single crystal structure to form a first, second and third layer of single crystal semiconductor material. A dielectric layer is formed that completely surrounds each single crystal region. A blocking layer is applied to prevent ion implantation where not desired. Ions are implanted into a predefined implant area. The semiconductor wafer is heated to create a dielectric layer part way through the single crystal semiconductor region. The second layer of single crystal semiconductor materials is formed by depositing a single crystal or polycrystalline material and annealing it to form a single crystal semiconductor. The deposited semiconductor layer is masked and etched to obtain single crystal regions directly above the previous layer. A blocking layer is applied and an ion implant is performed. After heating, there is left a region of single crystal silicon that has its sides and bottom surrounding by a dielectric border. The third layer of semiconductor material is likewise deposited and processed to form a top layer of single crystal semiconductor material.

公开(公告)号：US20050110110A1

公开(公告)日：2005-05-26

申请号：US10721524

申请日：2003-11-25

申请人： Richard Blanchard ,  Joseph McAlexander

发明人： Richard Blanchard ,  Joseph McAlexander

IPC分类号： G01P15/135 ,  B81B3/00 ,  B81C1/00 ,  G01K5/62 ,  G01P15/18 ,  H01L21/8238 ,  H01L29/82

CPC分类号： B81C1/00626 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81B2203/033 ,  B81C2201/0109 ,  B81C2201/014

摘要： A released beam structure fabricated in trench and manufacturing method thereof are provided herein. One embodiment of a released beam structure according to the present invention comprises a semiconductor substrate, a trench, a first conducting layer, and a beam. The trench extends into the semiconductor substrate and has walls. The first conducting layer is positioned over the walls of the trench at selected locations. The beam is positioned with the trench and is connected at a first portion thereof to the semiconductor substrate and movable at a second portion thereof. The second portion of the beam is spaced from the walls of the trench by a selected distance. Therefore, the second portion of the beam is free to move in a plane that is perpendicular or parallel to the surface of the substrate, and could be deflected to electrically contact with the walls of the trench in response to a predetermined acceleration force or a predetermined temperature variation applied on the beam structure. Other beam structures such as a beam held at both ends, or a beam held in the middle are also possible. Several beam structures at different angles can be fabricated simultaneously and mechanical etching stops are automatically formed to prevent unwanted overstress conditions when manufacturing several beam structures at the same time. Beam structures can also be manufactured in three orthogonal directions, providing information on acceleration in any direction.

摘要翻译： 本发明提供一种以沟槽制造的释放的束结构及其制造方法。 根据本发明的释放的光束结构的一个实施例包括半导体衬底，沟槽，第一导电层和光束。 沟槽延伸到半导体衬底中并具有壁。 第一导电层位于沟槽的选定位置的上方。 光束与沟槽定位并且在其第一部分处连接到半导体衬底并且可在其第二部分移动。 梁的第二部分与沟槽的壁间隔一定距离。 因此，梁的第二部分在垂直于或平行于衬底的表面的平面中自由移动，并且可以响应于预定的加速力或预定的加速力而被偏转以与沟槽的壁电接触 温度变化施加在梁结构上。 其他梁结构，例如保持在两端的梁或保持在中间的梁也是可能的。 可以同时制造不同角度的几个梁结构，并且自动形成机械蚀刻停止，以在同时制造几个梁结构时防止不想要的过应力条件。 梁结构也可以在三个正交方向上制造，提供关于任何方向上的加速度的信息。

公开(公告)号：US20090023260A9

公开(公告)日：2009-01-22

申请号：US11343329

申请日：2006-01-31

申请人： Richard Blanchard

发明人： Richard Blanchard

IPC分类号： H01L21/336

CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.

摘要翻译： 公开了一种制造半导体器件的方法，并且从在底部主表面上具有重掺杂N区并在顶部主表面上具有轻掺杂N区的半导体衬底开始。 衬底中存在多个沟槽，每个沟槽具有从顶部主表面朝向重掺杂区域延伸的第一延伸部分。 每个沟槽具有彼此平行对准的两个侧壁表面。 在每个沟槽的侧壁和底部上形成阻挡层。 然后将P型掺杂剂倾斜地注入到侧壁表面中以形成P型掺杂区域。 然后去除阻挡层。 然后蚀刻沟槽的底部以去除任何植入的P型掺杂剂。 植入物被扩散并且沟槽被填充。