公开(公告)号：US20150378411A1

公开(公告)日：2015-12-31

申请号：US14314790

申请日：2014-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron J. Grenat ,  Robert A. Hershberger ,  Sriram Sambamurthy ,  Samuel D. Naffziger ,  Christopher E. Tressler ,  Sho-Chien Kang ,  Joseph P. Shannon ,  Krishna Sai Bernucho ,  Ashwin Chincholi ,  Michael J. Austin ,  Steven F. Liepe ,  Umair B. Cheema

IPC: G06F1/28 ,  G06F1/26

CPC classification number: G01R19/0084 ,  G01R19/16552 ,  G01R31/40 ,  G01R35/005 ,  G06F1/26 ,  G06F1/32 ,  G06F11/3428 ,  G11C29/021 ,  G11C29/028 ,  G11C29/56012

Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.

Abstract translation: 处理系统包括用于测量与处理系统中的一个或多个位置相对应的一个或多个第一电压的一个或多个电源监视器（PSM）。 测量与执行一个或多个代码循环的处理系统同时执行。 处理系统还包括校准逻辑，用于基于参考电压和一个或多个第一电压的比较来修改提供给处理系统的第二电压。 基于由处理系统先前执行一个或多个代码循环来确定参考电压。

公开(公告)号：US10060955B2

公开(公告)日：2018-08-28

申请号：US14314790

申请日：2014-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron J. Grenat ,  Robert A. Hershberger ,  Sriram Sambamurthy ,  Samuel D. Naffziger ,  Christopher E. Tressler ,  Sho-Chien Kang ,  Joseph P. Shannon ,  Krishna Sai Bernucho ,  Ashwin Chincholi ,  Michael J. Austin ,  Steven F. Liepe ,  Umair B. Cheema

IPC: G06F1/26 ,  G01R19/00 ,  G06F1/32 ,  G11C29/02 ,  G11C29/56 ,  G06F11/34 ,  G01R31/40 ,  G01R35/00 ,  G01R19/165

CPC classification number: G01R19/0084 ,  G01R19/16552 ,  G01R31/40 ,  G01R35/005 ,  G06F1/26 ,  G06F1/32 ,  G06F11/3428 ,  G11C29/021 ,  G11C29/028 ,  G11C29/56012

Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.

公开(公告)号：US12113712B2

公开(公告)日：2024-10-08

申请号：US17032054

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Narendra Kamat ,  Vydhyanathan Kalyanasundharam ,  Gregg Donley ,  Ashwin Chincholi

IPC: H04L47/20 ,  G06F15/78 ,  H04L47/24 ,  H04L49/109

CPC classification number: H04L47/20 ,  G06F15/7825 ,  H04L47/24 ,  H04L49/109

Abstract: Dynamic network-on-chip traffic throttling, including: determining, by a detector module of a network-on-chip, that a predefined condition is met; sending, by the detector module, a signal to a mediator module of the network-on-chip; and sending, in response to the signal, by the mediator module, an indication to a plurality of agents to implement a traffic throttling policy.

公开(公告)号：US20220103489A1

公开(公告)日：2022-03-31

申请号：US17548398

申请日：2021-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Mark A. Silla ,  Ashwin Chincholi

IPC: H04L12/947 ,  H04L12/717 ,  H04L12/931 ,  H04L29/08 ,  H04L29/06

Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

公开(公告)号：US11223575B2

公开(公告)日：2022-01-11

申请号：US16725901

申请日：2019-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Mark A. Silla ,  Ashwin Chincholi

IPC: H04L12/947 ,  H04L12/717 ,  H04L12/931 ,  H04L29/08 ,  H04L29/06

Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

公开(公告)号：US20210194827A1

公开(公告)日：2021-06-24

申请号：US16725901

申请日：2019-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Mark A. Silla ,  Ashwin Chincholi

IPC: H04L12/947 ,  H04L12/931 ,  H04L12/717 ,  H04L29/06 ,  H04L29/08

Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.