公开(公告)号：US20190088626A1

公开(公告)日：2019-03-21

申请号：US16194265

申请日：2018-11-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/24 ,  H01L23/29 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.

公开(公告)号：US20180233457A1

公开(公告)日：2018-08-16

申请号：US15430355

申请日：2017-02-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU ,  Yu-Tzu PENG

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/367 ,  H01L23/29 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

公开(公告)号：US20180261573A1

公开(公告)日：2018-09-13

申请号：US15454520

申请日：2017-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L23/24 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/24 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.

公开(公告)号：US20180151478A1

公开(公告)日：2018-05-31

申请号：US15364139

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/4889 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/492 ,  H01L23/49527 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/4901 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/85

Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.