公开(公告)号：US10037974B2

公开(公告)日：2018-07-31

申请号：US15416907

申请日：2017-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chang Chi Lee ,  Chin-Li Kao ,  Dao-Long Chen ,  Ta-Chien Cheng

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3672 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.

公开(公告)号：US12107074B2

公开(公告)日：2024-10-01

申请号：US18115743

申请日：2023-02-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi Lee ,  Jung Jui Kang ,  Chiu-Wen Lee ,  Li Chieh Chen

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US12213247B2

公开(公告)日：2025-01-28

申请号：US17865380

申请日：2022-07-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jung Jui Kang ,  Chang Chi Lee

IPC: H05K1/02 ,  H05K1/14

Abstract: An electronic device is disclosed. The electronic device includes a carrier, a computing element disposed over the carrier, and a first data storage element disposed over the carrier and electrically connected with the computing element through the carrier. The computing element is configured to receive a first power provided from the first data storage element.

公开(公告)号：US10134677B1

公开(公告)日：2018-11-20

申请号：US15596956

申请日：2017-05-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Shih-Yu Wang ,  Chang Chi Lee

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5384 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L2221/68345 ,  H01L2221/68359

Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

公开(公告)号：US11991827B2

公开(公告)日：2024-05-21

申请号：US17966701

申请日：2022-10-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Yen Ting ,  Pao-Nan Lee ,  Hung-Chun Kuo ,  Jung Jui Kang ,  Chang Chi Lee

IPC: H05K1/14

CPC classification number: H05K1/141

Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.

公开(公告)号：US11967559B2

公开(公告)日：2024-04-23

申请号：US17535400

申请日：2021-11-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi Lee ,  Chiu-Wen Lee ,  Jung Jui Kang

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.

公开(公告)号：US11594518B2

公开(公告)日：2023-02-28

申请号：US17338600

申请日：2021-06-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi Lee ,  Jung Jui Kang ,  Chiu-Wen Lee ,  Li Chieh Chen

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US09917043B2

公开(公告)日：2018-03-13

申请号：US15479074

申请日：2017-04-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Chang Chi Lee ,  Chih-Pin Hung

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06586

Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.

公开(公告)号：US12176305B2

公开(公告)日：2024-12-24

申请号：US17676093

申请日：2022-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan Lee ,  Chen-Chao Wang ,  Chang Chi Lee

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/64 ,  H01L25/065

Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.

公开(公告)号：US12156336B2

公开(公告)日：2024-11-26

申请号：US17856898

申请日：2022-07-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chiung-Ying Kuo ,  Hung-Chun Kuo ,  Pao-Nan Lee ,  Jung Jui Kang ,  Chang Chi Lee

IPC: H05K1/18 ,  H05K1/02

Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.