公开(公告)号：US20210257331A1

公开(公告)日：2021-08-19

申请号：US16793991

申请日：2020-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yun-Ching HUNG ,  Yung-Sheng LIN ,  Chin-Li KAO

IPC: H01L23/00

Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

公开(公告)号：US20240297086A1

公开(公告)日：2024-09-05

申请号：US18116268

申请日：2023-03-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Wei CHIANG ,  Yun-Ching HUNG ,  Yung-Sheng LIN

IPC: H01L23/10 ,  H01L21/50

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: An interconnection structure and a package structure are provided. The interconnection structure includes a substrate, a conductive layer, a bonding layer, and a moderating layer. The conductive layer is over the substrate and has a top surface. The bonding layer is over the top surface of the conductive layer. The moderating layer is between the conductive layer and the bonding layer and configured to mitigate an increase in a surface roughness of the top surface of the conductive layer during an electroless plating process for forming the bonding layer.

公开(公告)号：US20220148989A1

公开(公告)日：2022-05-12

申请号：US17092195

申请日：2020-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Sheng LIN ,  Yun-Ching HUNG ,  An-Hsuan HSU ,  Chung-Hung LAI

IPC: H01L23/00

Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.