公开(公告)号：US08580642B1

公开(公告)日：2013-11-12

申请号：US13476645

申请日：2012-05-21

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66795

摘要： One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

摘要翻译： 本文公开的一种说明性方法包括通过图案化的硬掩模层执行第一蚀刻工艺，以在衬底中限定多个间隔开的沟槽，其限定用于器件的鳍片的第一部分，在沟槽中形成绝缘材料层 以及对所述绝缘材料层进行平坦化处理以暴露所述图案化的硬化物，执行第二蚀刻工艺以去除所述硬掩模层并且在所述绝缘材料层内限定空腔，在所述空腔内形成所述翅片的第二部分 ，其中所述翅片的第二部分由与所述基板不同的半导体材料构成，并且对所述绝缘材料层进行第三蚀刻工艺，使得所述绝缘材料的上表面在所述第二部分的上表面下方 鳍的一部分。

公开(公告)号：US08673718B2

公开(公告)日：2014-03-18

申请号：US13544259

申请日：2012-07-09

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/335

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

摘要翻译： 一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分 并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定 空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面 绝缘材料在第三部分的上表面下方。

公开(公告)号：US20130309847A1

公开(公告)日：2013-11-21

申请号：US13476645

申请日：2012-05-21

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/20

CPC分类号： H01L29/66795

摘要： One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

摘要翻译： 本文公开的一种说明性方法包括通过图案化的硬掩模层执行第一蚀刻工艺，以在衬底中限定多个间隔开的沟槽，其限定用于器件的鳍片的第一部分，在沟槽中形成绝缘材料层 以及对所述绝缘材料层进行平坦化处理以暴露所述图案化的硬化物，执行第二蚀刻工艺以去除所述硬掩模层并且在所述绝缘材料层内限定空腔，在所述空腔内形成所述翅片的第二部分 ，其中所述翅片的第二部分由与所述基板不同的半导体材料构成，并且对所述绝缘材料层进行第三蚀刻工艺，使得所述绝缘材料的上表面在所述第二部分的上表面下方 鳍的一部分。

公开(公告)号：US08669186B2

公开(公告)日：2014-03-11

申请号：US13359197

申请日：2012-01-26

申请人： Nicholas V. LiCausi

发明人： Nicholas V. LiCausi

IPC分类号： H01L21/311

CPC分类号： H01L27/1104 ,  H01L21/823821 ,  H01L21/845

摘要： In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.

摘要翻译： 在一个示例中，该方法包括在半导体衬底上形成硬掩模层，在硬掩模层之上形成图案化间隔物掩模层，其中图案化间隔物掩模层由多个第一间隔物，第二间隔物和第三间隔物组成， 以及通过所述图案化间隔掩模层对所述硬掩模层执行第一蚀刻工艺以限定图案化的硬掩模层。 该方法还包括通过图案化的硬掩模层执行第二蚀刻工艺，以在衬底中限定多个第一散热片，第二散热片和第三散热片，其中第一散热片的宽度大致对应于第一间隔件的宽度， 第二散热片具有大致对应于第二间隔件的宽度的宽度，并且第三散热片具有大致对应于第三间隔件的宽度的宽度。

公开(公告)号：US08557675B2

公开(公告)日：2013-10-15

申请号：US13305303

申请日：2011-11-28

申请人： Nicholas V. LiCausi

发明人： Nicholas V. LiCausi

IPC分类号： H01L29/06 ,  H01L21/033

CPC分类号： H01L21/0337 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure.

摘要翻译： 本文公开了使用多侧壁图像转移技术在结构中形成特征的方法，例如用于形成集成电路器件或半导体衬底的材料层。 在一个示例中，该方法包括在结构之上形成第一心轴，形成与第一心轴相邻的多个第一间隔件，邻近第一间隔件之一形成多个第二心轴，并且形成多个第二间隔件， 第二个心轴 该方法还包括执行至少一个蚀刻工艺，以相对于第一间隔件和第二间隔件选择性地移除第一心轴和第二心轴，从而限定由第一间隔件和第二间隔件组成的蚀刻掩模，并执行至少一个蚀刻 通过结构上的蚀刻掩模处理以在结构中限定多个特征。

公开(公告)号：US20130196508A1

公开(公告)日：2013-08-01

申请号：US13359197

申请日：2012-01-26

申请人： Nicholas V. LiCausi

发明人： Nicholas V. LiCausi

IPC分类号： H01L21/308

CPC分类号： H01L27/1104 ,  H01L21/823821 ,  H01L21/845

摘要： In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.

摘要翻译： 在一个示例中，该方法包括在半导体衬底上形成硬掩模层，在硬掩模层之上形成图案化间隔物掩模层，其中图案化间隔物掩模层由多个第一间隔物，第二间隔物和第三间隔物组成， 以及通过所述图案化间隔掩模层对所述硬掩模层执行第一蚀刻工艺以限定图案化的硬掩模层。 该方法还包括通过图案化的硬掩模层执行第二蚀刻工艺，以在衬底中限定多个第一散热片，第二散热片和第三散热片，其中第一散热片的宽度大致对应于第一间隔件的宽度， 第二散热片具有大致对应于第二间隔件的宽度的宽度，并且第三散热片具有大致对应于第三间隔件的宽度的宽度。

公开(公告)号：US20130134486A1

公开(公告)日：2013-05-30

申请号：US13305303

申请日：2011-11-28

申请人： Nicholas V. LiCausi

发明人： Nicholas V. LiCausi

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L21/0337 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure.

摘要翻译： 本文公开了使用多侧壁图像转移技术在结构中形成特征的方法，例如用于形成集成电路器件或半导体衬底的材料层。 在一个示例中，该方法包括在结构之上形成第一心轴，形成与第一心轴相邻的多个第一间隔件，邻近第一间隔件之一形成多个第二心轴，并且形成多个第二间隔件， 第二个心轴 该方法还包括执行至少一个蚀刻工艺，以相对于第一间隔件和第二间隔件选择性地移除第一心轴和第二心轴，从而限定由第一间隔件和第二间隔件组成的蚀刻掩模，并执行至少一个蚀刻 通过结构上的蚀刻掩模处理以在结构中限定多个特征。