公开(公告)号：US08580642B1

公开(公告)日：2013-11-12

申请号：US13476645

申请日：2012-05-21

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66795

摘要： One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

摘要翻译： 本文公开的一种说明性方法包括通过图案化的硬掩模层执行第一蚀刻工艺，以在衬底中限定多个间隔开的沟槽，其限定用于器件的鳍片的第一部分，在沟槽中形成绝缘材料层 以及对所述绝缘材料层进行平坦化处理以暴露所述图案化的硬化物，执行第二蚀刻工艺以去除所述硬掩模层并且在所述绝缘材料层内限定空腔，在所述空腔内形成所述翅片的第二部分 ，其中所述翅片的第二部分由与所述基板不同的半导体材料构成，并且对所述绝缘材料层进行第三蚀刻工艺，使得所述绝缘材料的上表面在所述第二部分的上表面下方 鳍的一部分。

公开(公告)号：US20140011341A1

公开(公告)日：2014-01-09

申请号：US13544259

申请日：2012-07-09

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

摘要翻译： 一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分 并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定 空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面 绝缘材料在第三部分的上表面下方。

公开(公告)号：US08673718B2

公开(公告)日：2014-03-18

申请号：US13544259

申请日：2012-07-09

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/335

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

摘要翻译： 一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分 并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定 空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面 绝缘材料在第三部分的上表面下方。

公开(公告)号：US20130309847A1

公开(公告)日：2013-11-21

申请号：US13476645

申请日：2012-05-21

申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. LiCausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

IPC分类号： H01L21/20

CPC分类号： H01L29/66795

摘要： One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

摘要翻译： 本文公开的一种说明性方法包括通过图案化的硬掩模层执行第一蚀刻工艺，以在衬底中限定多个间隔开的沟槽，其限定用于器件的鳍片的第一部分，在沟槽中形成绝缘材料层 以及对所述绝缘材料层进行平坦化处理以暴露所述图案化的硬化物，执行第二蚀刻工艺以去除所述硬掩模层并且在所述绝缘材料层内限定空腔，在所述空腔内形成所述翅片的第二部分 ，其中所述翅片的第二部分由与所述基板不同的半导体材料构成，并且对所述绝缘材料层进行第三蚀刻工艺，使得所述绝缘材料的上表面在所述第二部分的上表面下方 鳍的一部分。

公开(公告)号：US09564367B2

公开(公告)日：2017-02-07

申请号：US13613508

申请日：2012-09-13

申请人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

发明人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC分类号： H01L21/8234 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

摘要翻译： 本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后 形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

公开(公告)号：US20140070322A1

公开(公告)日：2014-03-13

申请号：US13613508

申请日：2012-09-13

申请人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

发明人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC分类号： H01L21/20 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

摘要翻译： 本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后 形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

公开(公告)号：US08502283B2

公开(公告)日：2013-08-06

申请号：US11926655

申请日：2007-10-29

申请人： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

发明人： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

摘要翻译： 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US07306997B2

公开(公告)日：2007-12-11

申请号：US10986399

申请日：2004-11-10

申请人： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

发明人： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

摘要翻译： 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US07078299B2

公开(公告)日：2006-07-18

申请号：US10654631

申请日：2003-09-03

申请人： Witold P. Maszara ,  Jung-Suk Goo ,  James N. Pan ,  Qi Xiang

发明人： Witold P. Maszara ,  Jung-Suk Goo ,  James N. Pan ,  Qi Xiang

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  A61F5/3776 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S438/933

摘要： A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.

摘要翻译： 使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成 特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

公开(公告)号：US06630720B1

公开(公告)日：2003-10-07

申请号：US10036210

申请日：2001-12-26

申请人： Witold P. Maszara ,  HaiHong Wang ,  Qi Xiang

发明人： Witold P. Maszara ,  HaiHong Wang ,  Qi Xiang

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L21/0337 ,  H01L21/84 ,  H01L27/1203

摘要： An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.

摘要翻译： 非对称半导体器件和制造一对不对称器件的方法。 半导体器件包括具有源极和漏极的半导体材料层，以及设置在半导体材料层上以限定插入在源极和漏极之间的沟道的双功函数栅极。