公开(公告)号：US5654931A

公开(公告)日：1997-08-05

申请号：US213531

申请日：1994-03-16

申请人： Akihiro Tamba ,  Masahiro Iwamura ,  Yutaka Kobayashi ,  Kinya Mitsumoto ,  Tatsumi Yamauchi ,  Shuko Yamauchi ,  Takashi Akioka

发明人： Akihiro Tamba ,  Masahiro Iwamura ,  Yutaka Kobayashi ,  Kinya Mitsumoto ,  Tatsumi Yamauchi ,  Shuko Yamauchi ,  Takashi Akioka

IPC分类号： G11C7/22 ,  G11C13/00

CPC分类号： G11C7/22

摘要： A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved. Another feature is that either the input/output pads of the data into or out of the semiconductor integrated circuit device or their accompanying circuit units are distributed in the semiconductor integrated circuit device. The individual features described above can be used solely or in combination, if necessary, to achieve the above-specified objects.

摘要翻译： 半导体集成电路器件被分成多个块，它们分别配备有信号生成单元，使得信号生成单元分布在半导体集成电路器件中。 优选地，半导体集成电路器件被构造为在对数据和控制信号进行了所有初始逻辑运算之后，通过针对各个块提供的脉冲产生单元产生脉冲信号。 由于这种结构，例如，SRAM可以将其写恢复时间最小化为0，从而可以实现高速操作。 此外，由于为每个块提供预编码器，所以可以减少芯片中的布线数量和面积，以提高半导体集成电路器件的集成度。 此外，芯片中的信号延迟和偏斜可以降低，从而可以实现高速度。 另一个特征是将半导体集成电路器件的数据的输入/输出焊盘或其相应的电路单元分布在半导体集成电路器件中。 如果需要，可以单独地或组合地使用上述各个特征来实现上述目的。

公开(公告)号：US5268587A

公开(公告)日：1993-12-07

申请号：US786750

申请日：1991-11-01

申请人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

发明人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region. A high impurity conductivity type buried third semiconductor region underlies the said second semiconductor region, and is formed by the same layer as a region isolating the bipolar transistors. This third region is disposed at the bottom surface of said first semiconductor region. A fourth semiconductor region of the second conductivity type is also formed in said first semiconductor region by the same layer used for collector contact regions of the bipolar transistors, and is connected with another end portion of said second semiconductor region, in contact with the third semiconductor region. The fourth semiconductor region is coupled to the input stage circuit, and the third and fourth semiconductor regions form a second PN junction diode.

摘要翻译： 半导体集成电路器件包括耦合到外部端子的绝缘击穿防止电路，用于保护输入级电路。 防止电路具有双极晶体管和互补MISFET，其包括第一导电类型的第一MISFET和第二导电类型的第二MISFET。 第一导电类型的第一半导体区域由与其中形成第二MISFET的阱区相同的层形成。 第二导电类型的第二半导体区域通过与第二MISFET的源极和漏极区域相同的层在所述第一半导体区域中形成。 这些第一和第二半导体区域形成第一PN结二极管。 外部端子电耦合到所述第二半导体区域的一个端部。 高杂质导电型掩埋的第三半导体区域位于所述第二半导体区域的下方，并且由与隔离双极晶体管的区域相同的层形成。 该第三区域设置在所述第一半导体区域的底表面。 第二导电类型的第四半导体区域也通过与用于双极晶体管的集电极接触区域的相同的层形成在所述第一半导体区域中，并且与所述第二半导体区域的与第三半导体接触的另一个端部连接 地区。 第四半导体区域耦合到输入级电路，并且第三和第四半导体区域形成第二PN结二极管。

公开(公告)号：US5121185A

公开(公告)日：1992-06-09

申请号：US253666

申请日：1988-10-05

申请人： Akihiro Tamba ,  Yutaka Kobayashi

发明人： Akihiro Tamba ,  Yutaka Kobayashi

IPC分类号： H01L27/06

CPC分类号： H01L27/0623

摘要： A monolithic semiconductor integrated circuit device includes bipolar transistors and MOS transistors constituting plural blocks formed in a single semiconductor substrate and capable of performing different functions. The bipolar transistors in the blocks have different breakdown voltages and different operation speeds due to the selection of different resistances of their collector regions.

摘要翻译： 单片半导体集成电路器件包括双极晶体管和MOS晶体管，其构成在单个半导体衬底中形成的能够执行不同功能的多个块。 由于选择其集电极区域的不同电阻，块中的双极晶体管具有不同的击穿电压和不同的操作速度。

公开(公告)号：US5604417A

公开(公告)日：1997-02-18

申请号：US992448

申请日：1992-12-17

申请人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

发明人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

IPC分类号： H01L27/06 ,  H03K19/013 ,  H03R19/013

CPC分类号： H01L27/0623 ,  H03K19/0136

摘要： The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors. Arrangements of circuits can also be effected in which the totem-pole connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side. With such circuit configurations, the output signal swing is maximized, and the differentiator circuit provides for temporary saturation along with a quickened recovery therefrom, thereby reducing transmission delay time and achieving low power consumption. The device can be implemented by circuitry which employs the bootstrap effect as well as IIL (I.sup.2 L) design schemes.

摘要翻译： 该装置在单个基板上具有多个内部电路，用于接收外部输入信号并将其输出到内部电路的多个输入电路，以及用于接收从内部电路输出并从外部输出信号的多个输出电路，其中 至少一个电路包括位于电源端侧的第一NPN双极晶体管的图腾柱输出级和位于地侧的第二NPN双极晶体管; 用于向第一NPN晶体管的基极提供脉冲作用的第一微分电路; 一对用于可控地驱动第二NPN晶体管的串联PMOS晶体管; 以及用于加速输出级晶体管关断的反馈MOS晶体管。 电路可以用第二微分电路代替串联连接的一对PMOS晶体管。 还可以实现电路的布置，其中图腾柱连接由PNP晶体管，电源端侧和地面或下拉侧的NPN或NMOS晶体管构成。 利用这种电路配置，输出信号摆幅最大化，微分电路提供临时饱和以及快速恢复，从而减少传输延迟时间并实现低功耗。 该设备可以由采用自举效应以及IIL（I2L）设计方案的电路来实现。

公开(公告)号：US5258644A

公开(公告)日：1993-11-02

申请号：US918133

申请日：1992-07-23

申请人： Akihiro Tamba ,  Yutaka Kobayashi ,  Tetsurou Matsumoto

发明人： Akihiro Tamba ,  Yutaka Kobayashi ,  Tetsurou Matsumoto

IPC分类号： H01L29/735 ,  H01L29/00

CPC分类号： H01L29/735

摘要： An improved bipolar transistor is provided which can be formed using a number of process steps which are similar to those used for forming MOSFETs. As such, the bipolar transistor is particularly useful in BiCMOS device arrangements. In accordance with one embodiment, a bipolar transistor is formed so that at least one of the emitter and collector regions has a high impurity region and a low impurity region. The collector and emitter regions of the device are formed in the base region to be spaced apart from one another, and the base electrode is arranged to cover the area of the base region between them. In an alternative embodiment, two collector regions can be provided in a base region on opposite sides of an emitter which is also formed in the base region. Two base electrodes can then be respectively provided in the areas between the two collectors and the emitter region. The bipolar transistors are particularly useful for forming a horizontal bipolar transistor structure. Because the bipolar transistors can be formed using the same types of steps used in the manufacture of MOSFETs, the manufacturing costs of the device can be reduced without sacrificing operational capabilities. This is particularly true in the manufacture of BiCMOS devices because many simultaneous manufacturing steps can be used for manufacturing the bipolar transistors and the MOSFETs.

摘要翻译： 提供了一种改进的双极晶体管，其可以使用与用于形成MOSFET的那些类似的多个工艺步骤形成。 因此，双极晶体管在BiCMOS器件布置中特别有用。 根据一个实施例，形成双极晶体管，使得发射极和集电极区域中的至少一个具有高杂质区域和低杂质区域。 器件的集电极和发射极区域形成在基极区域中以彼此间隔开，并且基极布置成覆盖它们之间的基极区域的区域。 在替代实施例中，两个集电极区域可以设置在也形成在基极区域中的发射极的相对侧上的基极区域中。 然后可以在两个集电极和发射极区域之间的区域中分别提供两个基极。 双极晶体管特别适用于形成水平双极晶体管结构。 因为可以使用与制造MOSFET相同类型的步骤来形成双极晶体管，所以可以降低器件的制造成本而不牺牲操作能力。 在BiCMOS器件的制造中尤其如此，因为许多同时的制造步骤可用于制造双极晶体管和MOSFET。

公开(公告)号：US5663659A

公开(公告)日：1997-09-02

申请号：US488441

申请日：1995-06-07

申请人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

发明人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

IPC分类号： H01L27/06 ,  H03K19/013 ,  H03K19/01

CPC分类号： H01L27/0623 ,  H03K19/0136

摘要： The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form. This type of arrangement is used to effect a BiNMOS type of logic (inverter) circuit. In accordance with another structural scheme, in place of the first CMOS logic gate, a BiCMOS type of arrangement is effected in combination with the second CMOS logic gate and differentiator.

摘要翻译： 半导体IC器件具有由具有输入和输出端子的第一CMOS逻辑门和与第一CMOS逻辑门执行相同逻辑运算的第二CMOS逻辑门构成的电路装置，该第二CMOS逻辑门的输入端连接到 第一个CMOS逻辑门的输入端。 该装置还需要一个其输入端连接到第二CMOS逻辑门的输出端并具有连接到第一CMOS逻辑门的输出端的输出端的微分电路。 通过这样的布置，有效栅极传播延迟时间对输出负载的依赖性降低。 结果，因此，可以在确保高操作速度以及低功耗的同时，使用低电源电压来实现该配置。 CMOS逻辑门也可以与以射极跟随器电路形式连接的NPN双极晶体管结合起来。 这种类型的布置用于实现BiNMOS类型的逻辑（逆变器）电路。 根据另一结构方案，代替第一CMOS逻辑门，与第二CMOS逻辑门和微分器结合实现BiCMOS类型的布置。

公开(公告)号：US5614848A

公开(公告)日：1997-03-25

申请号：US482570

申请日：1995-06-07

申请人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

发明人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

IPC分类号： H01L27/06 ,  H03K19/013 ,  H03K19/01

CPC分类号： H01L27/0623 ,  H03K19/0136

摘要： The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.

摘要翻译： 半导体IC器件具有这样的电路结构，其中一个或多个电路，例如在单个衬底上，包括由互补MOS电路的布置驱动的双极晶体管的图腾柱串联连接， 实现速度逻辑/切换操作。 还可以实现电路的布置，其中图腾柱串联连接由在电源端侧的PNP晶体管，以及在其接地或下拉侧上的NPN或NMOS晶体管构成。 通过这样的配置，可以在低工作电压下的输出信号摆幅最大化，同时实现相同的传播延迟时间和低功耗。 该装置还可以通过使用电容自举效应的电路以及IIL（I2L）设计方案来实现。

公开(公告)号：US5081515A

公开(公告)日：1992-01-14

申请号：US496328

申请日：1990-03-20

申请人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

发明人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/732

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.

摘要翻译： 半导体集成电路器件配备有DRAM，其存储单元形成为存储单元选择MISFET和层叠结构的数据存储电容元件的串联电路。 互补数据线通过连接到存储单元选择MISFET的半导体区域的层间绝缘膜在层叠结构的数据存储电容元件的上电极层上延伸。 为了减小寄生电容，互补数据线的布线宽度形成为小于互补数据线与层叠结构的数据存储电容元件的上电极层之间的层间绝缘膜的膜厚度。

公开(公告)号：US07983044B2

公开(公告)日：2011-07-19

申请号：US12684294

申请日：2010-01-08

申请人： Takayoshi Nakamura ,  Akihiro Tamba ,  Ryuichi Saito ,  Atsuo Nishihara

发明人： Takayoshi Nakamura ,  Akihiro Tamba ,  Ryuichi Saito ,  Atsuo Nishihara

IPC分类号： H05K7/20 ,  F28F7/00 ,  H02G3/03 ,  H01L23/34 ,  B60K1/00

CPC分类号： H05K7/20927 ,  B60H1/00392 ,  B60H1/00428 ,  B60L15/007 ,  B60L2240/525 ,  H01L23/473 ,  H01L2924/0002 ,  H02M7/003 ,  Y02T10/645 ,  Y02T10/88 ,  H01L2924/00

摘要： An inverter apparatus includes a liquid path in which cooling water flows, and in which the cooling water performs cooling at a cooling part located directly underneath the power circuit part of the inverter apparatus. The liquid path includes a first partial structure part formed between a feed pipe and the cooling part, and having a liquid path cross-sectional profile that is gradually reduced in the short-side direction of the cooling part and that is gradually enlarged in the long-side direction thereof; and a second partial structure part formed between the cooling part and a drain pipe, and having a liquid path cross-sectional profile that is gradually enlarged from the short-side of the cooling part and that is gradually reduced from the long-side thereof.

摘要翻译： 逆变器装置包括冷却水流动的液体通路，冷却水在逆变器装置的电源电路部正下方的冷却部进行冷却。 液体路径包括形成在供给管和冷却部之间的第一部分结构部分，并且具有在冷却部的短边方向上逐渐减小的液体流路横截面轮廓，并且在长度方向上逐渐变大 的方向; 以及第二部分结构部分，其形成在冷却部分和排水管之间，并且具有从冷却部分的短边逐渐增大并且从其长边逐渐减小的液体流路横截面轮廓。

公开(公告)号：US06486548B1

公开(公告)日：2002-11-26

申请号：US09529800

申请日：2000-04-20

申请人： Kinya Nakatsu ,  Toshio Ogawa ,  Akihiro Tamba ,  Hiroshi Fujii ,  Hiroyuki Tomita ,  Norinaga Suzuki ,  Kazuhiro Ito ,  Masahiro Hiraga

发明人： Kinya Nakatsu ,  Toshio Ogawa ,  Akihiro Tamba ,  Hiroshi Fujii ,  Hiroyuki Tomita ,  Norinaga Suzuki ,  Kazuhiro Ito ,  Masahiro Hiraga

IPC分类号： H01L2348

CPC分类号： H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/01078 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/1627 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor module in which a lead electrode is integrally formed with or pressed into resin separated from a resin case, and a connector securing a pad for bonding a metal wire to the lead electrode is bonded to a substrate with a power semiconductor element mounted thereon by an adhesive, and the like in a similar manner as the module case. According to the present invention, an electrode can be disposed in an appropriate position in the semiconductor module, and the scope of the free layout is enhanced.

摘要翻译： 一种半导体模块，其中引线电极与树脂壳体分离的树脂整体形成或压制成树脂，并且将固定用于将金属线接合到引线电极的焊盘的连接器接合到具有安装在其上的功率半导体元件的基板上， 粘合剂等，以与模块壳体相似的方式。 根据本发明，电极可以设置在半导体模块中的适当位置，并且增加了自由布局的范围。