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    Method of fabricating a CMOS semiconductor devices
    1.
    发明授权
    Method of fabricating a CMOS semiconductor devices 失效
    制造CMOS半导体器件的方法

    公开(公告)号：US5273914A

    公开(公告)日：1993-12-28

    申请号：US900743

    申请日：1992-06-19

    申请人： Akio Miyajima ,  Keiichi Kagawa ,  Akihira Shinohara ,  Kiyoyuki Morita ,  Takashi Uehara

    发明人： Akio Miyajima ,  Keiichi Kagawa ,  Akihira Shinohara ,  Kiyoyuki Morita ,  Takashi Uehara

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/266

    CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0928 ,  Y10S148/015

    摘要： An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from being exposed to ion implantation. The prevention of the exposure of the gate electrode to the ion implantation ensures the prevention of channeling in the gate electrode. The invention includes forming a first protective film on the gate of an NMOS, implanting to form LDD region for the NMOS, implanting to form source and drain regions of a PMOS, forming a second protective film on the gate of the NMOS, implanting to form source and drain regions of the NMOS, the first and second protective films prevent the gate electrode of the NMOS from being exposed to ion implantation during the respective implanting steps so that channeling is prevented from occurring in the gate electrode of the NMOS.

    摘要翻译： 在基板上延伸的栅电极上形成离子注入阻挡层。 当将离子注入到衬底中以在衬底中形成LDD层或源极和漏极区域时，阻挡层用于防止栅电极暴露于离子注入。 防止栅电极暴露于离子注入确保防止栅电极中的沟道化。 本发明包括在NMOS的栅极上形成第一保护膜，注入以形成用于NMOS的LDD区，注入以形成PMOS的源极和漏极区，在NMOS的栅极上形成第二保护膜，以形成 源极和漏极区域中，第一和第二保护膜防止NMOS的栅电极在相应的注入步骤期间暴露于离子注入，从而防止在NMOS的栅电极中发生沟道化。

    Semiconductor apparatus having an n-channel MOS transistor and a p-channel MOS transistor and method for manufacturing the semiconductor apparatus
    3.
    发明授权
    Semiconductor apparatus having an n-channel MOS transistor and a p-channel MOS transistor and method for manufacturing the semiconductor apparatus 失效
    具有n沟道MOS晶体管和p沟道MOS晶体管的半导体装置及其制造方法

    公开(公告)号：US5498908A

    公开(公告)日：1996-03-12

    申请号：US380460

    申请日：1995-01-30

    申请人： Takashi Nakabayashi ,  Takashi Uehara ,  Akihira Shinohara

    发明人： Takashi Nakabayashi ,  Takashi Uehara ,  Akihira Shinohara

    IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L23/48

    CPC分类号： H01L21/823842 ,  H01L21/823871 ,  H01L29/4933

    摘要： A semiconductor apparatus with MOS transistors for transmitting electrons from an n type source layer to an n type drain layer through a first channel region in an n-channel MOS transistor and transmitting holes from a p type source layer to a p type drain layer through a second channel region in a p-channel MOS transistor consists of a field oxide layer for separating the n-channel MOS transistor from the p-channel MOS transistor, an n type gate electrode mounted on a first gate oxide film arranged on the first channel region, a p type gate electrode mounted on a second gate oxide film arranged on the second channel region and positioned far away from the n type gate electrode to prevent impurities implanted into one of tile gate electrodes from diffusing into the other gate electrode, and a gate metal wiring connecting the gate electrodes through a gate contact hole to miniaturize the transistors.

    摘要翻译： 一种具有MOS晶体管的半导体器件，用于通过n沟道MOS晶体管中的第一沟道区将电子从n型源极层传输到n型漏极层，并且通过第二沟道将空穴从ap型源极层传输到ap型漏极层 p沟道MOS晶体管的区域由用于从p沟道MOS晶体管分离n沟道MOS晶体管的场氧化物层，安装在布置在第一沟道区上的第一栅氧化膜上的n型栅电极， 型栅电极，其安装在布置在第二沟道区上并位于远离n型栅电极的第二栅极氧化膜上，以防止注入到一块瓦栅电极中的杂质扩散到另一栅电极中;栅极金属布线连接 栅极通过栅极接触孔使晶体管小型化。

    Manufacturing method of CMOS transistor
    5.
    发明授权
    Manufacturing method of CMOS transistor 失效
    CMOS晶体管的制造方法

    公开(公告)号：US5756382A

    公开(公告)日：1998-05-26

    申请号：US784354

    申请日：1997-01-23

    申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    IPC分类号： H01L21/8238 ,  H01L21/265

    CPC分类号： H01L21/823814 ,  Y10S148/147

    摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

    摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

    Manufacturing method of CMOS transistor
    6.
    发明授权
    Manufacturing method of CMOS transistor 失效
    CMOS晶体管的制造方法

    公开(公告)号：US5726071A

    公开(公告)日：1998-03-10

    申请号：US789315

    申请日：1997-01-23

    申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    IPC分类号： H01L21/8238 ,  H01L21/70

    CPC分类号： H01L21/823814 ,  Y10S148/147

    摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

    摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的温度下对N型重掺杂扩散层进行第二次热处理。 使用P沟道晶体管的栅电极作为掩模来形成作为P沟道晶体管的源极或漏极的P型重掺杂扩散层。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

    Manufacturing method of CMOS transistor
    7.
    发明授权
    Manufacturing method of CMOS transistor 失效
    CMOS晶体管的制造方法

    公开(公告)号：US5686340A

    公开(公告)日：1997-11-11

    申请号：US723710

    申请日：1996-09-30

    申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    IPC分类号： H01L21/8238 ,  H01L21/265

    CPC分类号： H01L21/823814 ,  Y10S148/147

    摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

    摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的温度下对N型重掺杂扩散层进行第二次热处理。 使用P沟道晶体管的栅电极作为掩模来形成作为P沟道晶体管的源极或漏极的P型重掺杂扩散层。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。