公开(公告)号：US5985708A

公开(公告)日：1999-11-16

申请号：US816596

申请日：1997-03-13

申请人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L27/12 ,  H01L29/73 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8249

CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/7317 ,  H01L29/7394 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/78639 ,  H01L29/78645 ,  H01L29/78687

摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.

摘要翻译： 一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层， 所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极， 以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置 不同于第二导电型基底层，和多晶 半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

公开(公告)号：US5751022A

公开(公告)日：1998-05-12

申请号：US806153

申请日：1997-02-25

申请人： Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/749 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/7455

摘要： A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.

摘要翻译： 公开了具有耦合到半导体开关器件和半导体整流器的晶闸管区域的半导体器件。 在关断操作期间，从晶闸管区域的p型基极区域通过半导体整流器和晶闸管的阴极排出孔。 在导通期间，电子通过半导体开关器件从阴极电极提供给晶闸管的n型发射极区域。

公开(公告)号：US6064086A

公开(公告)日：2000-05-16

申请号：US72460

申请日：1998-05-05

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki ,  Norio Yasuhara

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki ,  Norio Yasuhara

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： An n-type buffer layer and a p-type base layer are formed in the surface of the n.sup.- -type drift layer. A p.sup.+ -type drain layer is formed in the surface of the n-type buffer layer. An n.sup.+ -type source layer and a p.sup.+ -type contact layer are formed in the surface of the p-type base layer. A main gate electrode is arranged to face, through a gate oxide film, a surface of the p-type base layer which is interposed between the n.sup.+ -type source layer and the n.sup.- -type drift layer. An n-type relay layer is formed in the surface of the n.sup.- -type drift layer to face the n.sup.+ -type source layer through the p-type base layer under the main gate electrode. The n-type relay layer extends from the n.sup.- -type drift layer into the p-type base layer. The n-type relay layer decreases the channel resistance.

摘要翻译： 在n型漂移层的表面形成n型缓冲层和p型基底层。 在n型缓冲层的表面形成p +型漏极层。 在p型基底层的表面形成n +型源极层和p +型接触层。 主栅极布置成通过栅极氧化膜面对介于n +型源极层和n型漂移层之间的p型基极层的表面。 在n型漂移层的表面形成n型继电器层，通过主栅电极下方的p型基极层面对n +型源极层。 n型继电器层从n型漂移层延伸到p型基极层。 n型继电器层降低了通道电阻。

公开(公告)号：US5640040A

公开(公告)日：1997-06-17

申请号：US481097

申请日：1995-06-07

申请人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura ,  Hideyuki Funaki

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/404 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286 ,  H01L29/78603 ,  H01L2924/0002

摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.

摘要翻译： 一种高耐压电压半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上并由第一导电类型的高电阻半导体形成的有源层，第一导电类型的第一杂质区 形成在有源层中的第二杂质区和形成在有源层中并与第一杂质区隔开预定距离的第二导电类型的第二杂质区。 第一杂质区由扩散层形成。 扩散层彼此叠加并且扩散深度或扩散窗宽度不同，或两者均不同。

公开(公告)号：US5592014A

公开(公告)日：1997-01-07

申请号：US484864

申请日：1995-06-07

申请人： Hideyuki Funaki ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura

发明人： Hideyuki Funaki ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/404 ,  H01L21/76264 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286 ,  H01L2924/0002

摘要： A high breakdown voltage semiconductor apparatus comprises a substrate having an insulating layer formed thereon, a high resistance semiconductor layer of a first conductivity type formed on said insulating layer, a base region of the first conductivity type formed selectively in a surface region of the high resistance semiconductor layer, a drift region of a second conductivity type formed selectively in the surface region of the high resistance semiconductor layer so as not to reach the insulating layer, a source region of the second conductivity type formed in the base region, a drain region formed in the drift region, a gate electrode formed on a region between the source region and the drift region, with a gate insulating film interposed between the gate electrode and the region between the source region and the drift region, a source electrode provided in contact with the base region and the source region, a drain electrode provided in contact with the drain region. The dosage of impurities in the high resistance semiconductor layer is 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2 and the dosage of impurities in the drift layer is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2.

摘要翻译： 一种高耐压电压半导体装置，包括：在其上形成有绝缘层的基板，形成在所述绝缘层上的第一导电类型的高电阻半导体层，所述第一导电类型的基极区选择性地形成在所述高电阻的表面区域中 半导体层，选择性地形成在高电阻半导体层的表面区域中以便不到达绝缘层的第二导电类型的漂移区域，形成在基极区域中的第二导电类型的源极区域，形成的漏极区域 在漂移区域中，形成在源极区域和漂移区域之间的区域上的栅电极，栅极绝缘膜插入在栅极电极和源极区域与漂移区域之间的区域中，源极电极与 所述基极区域和所述源极区域，设置成与所述漏极区域接触的漏极电极。 高电阻半导体层中的杂质用量为2×10 12 cm -2至3×10 12 cm -2，漂移层中的杂质用量为1×10 12 cm -2至2×10 12 cm -2。

公开(公告)号：US6163051A

公开(公告)日：2000-12-19

申请号：US154041

申请日：1998-09-16

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki ,  Norio Yasuhara

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki ,  Norio Yasuhara

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： A high breakdown voltage semiconductor device comprising a first base region of a first conductivity type, a second base region of a second conductivity type, which is formed in a surface region of the first base region, a first gate insulation film formed on an inner wall of a first LOCOS groove formed passing through the second base region to reach the first base region, a first gate electrode formed on the first gate insulation film, a first source region of a first conductivity type, which is formed in a surface region of the second base region around the first LOCOS groove in such a manner as to contact with the first gate insulating film, a first drain region formed in a surface region of the first base region in such a manner as to be spaced apart from the second base region, a source electrode formed on the first source region and on the second base region, and a drain electrode formed on the first drain region.

摘要翻译： 一种高耐压电压半导体器件，包括第一导电类型的第一基极区域和形成在第一基极区域的表面区域中的第二导电类型的第二基极区域，形成在内壁上的第一栅极绝缘膜 形成为穿过第二基极区域以到达第一基极区域的第一LOCOS沟槽，形成在第一栅极绝缘膜上的第一栅极电极，形成在第一栅极绝缘膜的表面区域中的第一导电类型的第一源极区域， 第二基区，以与第一栅极绝缘膜接触的方式围绕第一LOCOS沟槽;第一漏极区，形成在第一基极区域的表面区域中，以与第二基极区域隔开; 形成在第一源极区域和第二基极区域上的源电极以及形成在第一漏极区域上的漏电极。

公开(公告)号：US5438220A

公开(公告)日：1995-08-01

申请号：US085056

申请日：1993-07-02

申请人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura ,  Hideyuki Funaki

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

CPC分类号： H01L29/404 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286 ,  H01L29/78603 ,  H01L2924/0002

摘要： A high breakdown voltage semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.

摘要翻译： 高耐压半导体器件包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上并由第一导电类型的高电阻半导体形成的有源层，第一导电类型的第一杂质区 形成在有源层中的第二杂质区和形成在有源层中并与第一杂质区隔开预定距离的第二导电类型的第二杂质区。 第一杂质区由扩散层形成。 扩散层彼此叠加并且扩散深度或扩散窗宽度不同，或两者均不同。

公开(公告)号：US5343067A

公开(公告)日：1994-08-30

申请号：US829214

申请日：1992-01-31

申请人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

发明人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

CPC分类号： H01L29/404 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286

摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

摘要翻译： 一种高耐压半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上的高电阻半导体层，形成在高电阻半导体层中的隔离区，形成在高电阻半导体中的元件区 在横向方向上被隔离区域隔离的层，形成在元件区域的中心表面部分中的第一导电类型的第一低电阻区域和形成在元件区域的中心表面部分中的第二导电类型的第二低电阻区域， 元素区域。 元件区域中的杂质的剂量被设定为使得当在第一和第二低电阻区域之间施加电压时，第一低电阻区域和第二低电阻区域之间的元件区域的一部分被完全耗尽。

公开(公告)号：US5536961A

公开(公告)日：1996-07-16

申请号：US396794

申请日：1995-03-01

申请人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

发明人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L29/404 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286

摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

公开(公告)号：US5463231A

公开(公告)日：1995-10-31

申请号：US353385

申请日：1994-12-02

申请人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

发明人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

IPC分类号： H01L27/06 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L27/0617 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.