公开(公告)号：US07365392B2

公开(公告)日：2008-04-29

申请号：US11010508

申请日：2004-12-14

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L27/00

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

摘要翻译： 通过图案化同一多晶硅层形成TLPM的栅电极和平面器件的栅电极。 通过对相同的金属层进行构图，形成TLPM的漏极和源极，并且平面器件的漏电极和源电极形成。 因此，TLPM和平面器件可以通过所得的金属布线层和多​​晶硅层彼此电连接，而不需要在印刷电路板上进行引线接合。

公开(公告)号：US20080303087A1

公开(公告)日：2008-12-11

申请号：US12149016

申请日：2008-04-24

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

公开(公告)号：US20050087800A1

公开(公告)日：2005-04-28

申请号：US11010508

申请日：2004-12-14

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

公开(公告)号：US06858500B2

公开(公告)日：2005-02-22

申请号：US10334127

申请日：2002-12-31

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

摘要翻译： 通过图案化同一多晶硅层形成TLPM的栅电极和平面器件的栅电极。 通过对相同的金属层进行构图，形成TLPM的漏极和源极，并且平面器件的漏电极和源电极形成。 因此，TLPM和平面器件可以通过所得的金属布线层和多​​晶硅层彼此电连接，而不需要在印刷电路板上进行引线接合。

公开(公告)号：US20060110875A1

公开(公告)日：2006-05-25

申请号：US11329012

申请日：2006-01-10

申请人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

发明人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

IPC分类号： H01L21/8238

CPC分类号： H01L29/7825 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7809

摘要： A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

摘要翻译： 提供了一种半导体器件，其可以通过比用于80V击穿电压的常规横向沟槽功率MOSFET更简单的工艺制造，并且其具有比常规侧向功率MOSFET更小的器件间距和每单位面积的较低导通电阻 用于低于80V的击穿电压。 沿着沟槽的侧表面以均匀的厚度薄化地形成栅氧化膜。 然后，通过选择性氧化沿着沟槽的底表面形成栅极氧化膜，以便比沟槽的侧表面上的栅极氧化膜更厚，并且从底表面的边缘逐渐变厚 沟渠朝向多晶硅排水。

公开(公告)号：US07012301B2

公开(公告)日：2006-03-14

申请号：US10322367

申请日：2002-12-18

申请人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

发明人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7825 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7809

摘要： A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

摘要翻译： 提供了一种半导体器件，其可以通过比用于80V击穿电压的常规横向沟槽功率MOSFET更简单的工艺制造，并且其具有比常规侧向功率MOSFET更小的器件间距和每单位面积的较低导通电阻 用于低于80V的击穿电压。 沿着沟槽的侧表面以均匀的厚度薄化地形成栅氧化膜。 然后，通过选择性氧化沿着沟槽的底表面形成栅极氧化膜，以便比沟槽的侧表面上的栅极氧化膜更厚，并且从底表面的边缘逐渐变厚 沟渠朝向多晶硅排水。

公开(公告)号：US07256086B2

公开(公告)日：2007-08-14

申请号：US11329012

申请日：2006-01-10

申请人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

发明人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7825 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7809

摘要： A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

摘要翻译： 提供了一种半导体器件，其可以通过比用于80V击穿电压的常规横向沟槽功率MOSFET更简单的工艺制造，并且其具有比常规侧向功率MOSFET更小的器件间距和每单位面积的较低导通电阻 用于低于80V的击穿电压。 沿着沟槽的侧表面以均匀的厚度薄化地形成栅氧化膜。 然后，通过选择性氧化沿着沟槽的底表面形成栅极氧化膜，以便比沟槽的侧表面上的栅极氧化膜更厚，并且从底表面的边缘逐渐变厚 沟渠朝向多晶硅排水。

公开(公告)号：US07034377B2

公开(公告)日：2006-04-25

申请号：US10720738

申请日：2003-11-24

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/7825 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801

摘要： To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.

摘要翻译： 为了减小诸如沟槽横向功率MOSFET的半导体器件中的导通电阻，沟槽蚀刻区域形成网格图案，其中形成在有源区域中的第一沟槽部分和形成在栅极中的第二沟槽部分 用于将栅极多晶硅引出到衬底表面的区域彼此相交。 留下不经过蚀刻的岛状非沟槽区域通过与构成网状图案的第一和第二沟槽部分连接的一个或多个第三沟槽部分分成多个较小区域。 在每个非沟槽区域中，形成用于连接漏极区域（或源极区域）和电极的接触部分，以便扩展到非沟槽区域中的所有较小区域。

公开(公告)号：US08691619B2

公开(公告)日：2014-04-08

申请号：US12743686

申请日：2008-11-25

申请人： Hideki Hakuma ,  Katsuya Tabuchi ,  Yosuke Fujiwara ,  Katsumi Kushiya

发明人： Hideki Hakuma ,  Katsuya Tabuchi ,  Yosuke Fujiwara ,  Katsumi Kushiya

IPC分类号： H01L31/18

CPC分类号： H01L31/0749 ,  H01L31/0296 ,  H01L31/1836 ,  Y02E10/541 ,  Y02P70/521

摘要： This invention aims to provide a laminated structure and an integrated structure of a high production efficiency for a CIS based thin-film solar cell, which can produce a high-resistance buffer layer of the CIS based thin-film solar cell efficiently on a series of production lines and which needs no treatment of wastes or the like, and a manufacturing method for the structures. The CIS based thin-film solar cell includes a back electrode, a p-type CIS based light absorbing layer, a high-resistance buffer layer and an n-type transparent conductive film laminated in this order. The high-resistance buffer layer and the n-type transparent conductive film are formed of thin films of a zinc oxide group. The buffer layer contacts the p-type CIS based light absorbing layer directly, and has a resistivity of 500Ω·cm or higher.

摘要翻译： 本发明的目的在于提供一种用于CIS基薄膜太阳能电池的高生产效率的叠层结构和一体化结构，其可以在一系列的高分子材料上有效地生产CIS基薄膜太阳能电池的高电阻缓冲层 生产线并且不需要处理废物等，以及该结构的制造方法。 基于CIS的薄膜太阳能电池包括依次层叠的背面电极，p型CIS系的光吸收层，高电阻缓冲层和n型透明导电膜。 高电阻缓冲层和n型透明导电膜由氧化锌基团的薄膜形成。 缓冲层直接与p型CIS基光吸收层接触，电阻率为500Ω·cm·cm以上。

公开(公告)号：US20100311202A1

公开(公告)日：2010-12-09

申请号：US12745116

申请日：2008-11-28

申请人： Hideki Hakuma ,  Yuri Yamaguchi ,  Katsuya Tabuchi ,  Katsumi Kushiya

发明人： Hideki Hakuma ,  Yuri Yamaguchi ,  Katsuya Tabuchi ,  Katsumi Kushiya

IPC分类号： H01L31/18

CPC分类号： H01L31/0322 ,  H01L31/0749 ,  Y02E10/541 ,  Y02P70/521

摘要： A treatment object containing any one of Cu/Ga, Cu/In and Cu—Ga/In is held in a heated state at a temperature T1 for a time Δt1 in such a state that a selenium source is introduced, thereby forming a selenide. Thereafter, a sulfur source is introduced to replace the atmosphere in the system with a sulfur atmosphere. In this state, the treatment object is held in a heated state at a temperature T2 for a time Δt2. The temperature of the treatment object is then decreased to T3, and, at that temperature, the treatment object is held in a heated state for a time Δt3.

摘要翻译： 将包含Cu / Ga，Cu / In和Cu-Ga / In中的任一种的处理对象在导入硒源的状态下在T1的温度下保持一段时间＆lt; Dgr; t1，从而形成 硒化物 此后，引入硫源以用硫气氛代替系统中的气氛。 在这种状态下，处理对象在温度T2下保持在加热状态一段时间＆lt; Dgr; t2。 然后将处理对象的温度降低至T3，并且在该温度下，将处理对象保持在加热状态一段时间＆lt; Dgr; t3。