利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

187 条记录 (耗时 0.027 秒)

    NAND PRE-READ ERROR RECOVERY
    1.
    发明申请
    NAND PRE-READ ERROR RECOVERY 有权
    NAND预读错误恢复

    公开(公告)号：US20150378815A1

    公开(公告)日：2015-12-31

    申请号：US14314663

    申请日：2014-06-25

    申请人： Akira Goda ,  Pranav Kalavade ,  Charan Srinivasan

    发明人： Akira Goda ,  Pranav Kalavade ,  Charan Srinivasan

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2029/0411

    摘要： Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method may include applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method may further include determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.

    摘要翻译： 公开并描述了用于对NAND存储器件中的存储器页进行编程的技术。 在一个示例中，方法可以包括应用用于页面的较低页面编程和下部页面的预读数据的初始编程脉冲。 该方法还可以包括确定是否对下部页面的数据应用错误恢复操作。 存储表示用于编程上页数据的辅助编程脉冲的数据，并且基于次要编程脉冲和下部页面的数据对高位页数据进行编程。

    Memory program disturb reduction
    2.
    发明授权
    Memory program disturb reduction 有权
    存储器程序干扰减少

    公开(公告)号：US08982625B2

    公开(公告)日：2015-03-17

    申请号：US13600623

    申请日：2012-08-31

    申请人： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

    发明人： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

    摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

    摘要翻译： 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括在编程的第一次通过期间将第一偏置电压值应用于源极选择栅极以将存储器单元与源极隔离，在第一次处理期间将编程电压施加到存储器单元的页面的访问线 编程的通过，以及在源选择栅极施加第二偏置电压值以在第二次编程期间隔离存储器单元与源极。 公开了其它装置，系统和方法。

    MEMORY PROGRAM DISTURB REDUCTION
    3.
    发明申请
    MEMORY PROGRAM DISTURB REDUCTION 有权
    存储器程序减少干扰

    公开(公告)号：US20140063960A1

    公开(公告)日：2014-03-06

    申请号：US13600623

    申请日：2012-08-31

    申请人： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

    发明人： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

    摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

    摘要翻译： 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括在编程的第一次通过期间将第一偏置电压值应用于源极选择栅极以将存储器单元与源极隔离，在第一次处理期间将编程电压施加到存储器单元的页面的访问线 编程的通过，以及在源选择栅极施加第二偏置电压值以在第二次编程期间隔离存储器单元与源极。 公开了其它装置，系统和方法。

    DRAIN SELECT GATE VOLTAGE MANAGEMENT
    5.
    发明申请
    DRAIN SELECT GATE VOLTAGE MANAGEMENT 有权
    排水门电压管理

    公开(公告)号：US20110216600A1

    公开(公告)日：2011-09-08

    申请号：US12715530

    申请日：2010-03-02

    申请人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    发明人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/0433

    摘要： Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.

    摘要翻译： 一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值 在第二编程时间段的后续部分中，栅极电压与第一值不同。 漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。 第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。 公开了附加装置，系统和方法。

    Programming memory devices
    7.
    发明授权
    Programming memory devices 有权

    公开(公告)号：US10217515B2

    公开(公告)日：2019-02-26

    申请号：US15477048

    申请日：2017-04-01

    申请人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

    发明人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

    IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C8/08

    摘要： Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.

    Drain select gate voltage management
    8.
    发明授权
    Drain select gate voltage management 有权
    漏极选择栅极电压管理

    公开(公告)号：US08767487B2

    公开(公告)日：2014-07-01

    申请号：US12715530

    申请日：2010-03-02

    申请人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    发明人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    IPC分类号： G11C7/00

    CPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/0433

    摘要： Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.

    摘要翻译： 一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值 在第二编程时间段的后续部分中，栅极电压与第一值不同。 漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。 第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。 公开了附加装置，系统和方法。

    ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH
    9.
    发明申请
    ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH 有权
    用于垂直NAND闪存的擦除和软件程序

    公开(公告)号：US20140169093A1

    公开(公告)日：2014-06-19

    申请号：US13719558

    申请日：2012-12-19

    申请人： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

    发明人： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

    IPC分类号： G11C16/16

    CPC分类号： G11C16/16 ,  G11C8/12 ,  G11C16/04 ,  G11C16/3409 ,  G11C16/3445

    摘要： Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify

    摘要翻译： 擦除和/或软件编程NAND存储器块的方法和装置可以包括在包括两个或多个子块的NAND存储器块上执行擦除周期，验证两个或更多个子块直到子块失败 验证，停止验证以响应失败的验证，在NAND存储器块上执行另一个擦除周期，并重新启动以验证子块处的两个或更多个子块，验证失败